37//G-H are interconnect cols with different clock resources
38setFabricChar('G', 58, "INT/RCLK_INT_L"); //"INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT/RCLK_INT_L"
39setFabricChar('H', 58, "INT/RCLK_INT_R"); //"INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT + INT/RCLK_INT_R"
40
41//I-J are CLEL_R tiles with different clock resources