byteman  1.3 (Build #225)
Bitstream relocation and manipulation tool
inlineCAP.h
Go to the documentation of this file.
1 /******************************************************************************
2  * Copyright 2022 Kristiyan Manev (University of Manchester)
3  *
4  * Licensed under the Apache License, Version 2.0(the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  *****************************************************************************/
16 
17 #define FABRIC_SYNC_WORD 0xAA995566
18 
19 inline XCAP::Register getXCAPregister(std::string s)
20 {
21  if(str::iff::stringContains(s, "CRC"))
22  return XCAP::Register::CRC;
23  else if(str::iff::stringContains(s, "FAR"))
24  return XCAP::Register::FAR;
25  else if(str::iff::stringContains(s, "FDRI"))
26  return XCAP::Register::FDRI;
27  else if(str::iff::stringContains(s, "FDRO"))
28  return XCAP::Register::FDRO;
29  else if(str::iff::stringContains(s, "CTRL0"))
30  return XCAP::Register::CTRL0;
31  else if(str::iff::stringContains(s, "MASK"))
32  return XCAP::Register::MASK;
33  else if(str::iff::stringContains(s, "STAT"))
34  return XCAP::Register::STAT;
35  else if(str::iff::stringContains(s, "LOUT"))
36  return XCAP::Register::LOUT;
37  else if(str::iff::stringContains(s, "COR0"))
38  return XCAP::Register::COR0;
39  else if(str::iff::stringContains(s, "MFWR"))
40  return XCAP::Register::MFWR;
41  else if(str::iff::stringContains(s, "CBC"))
42  return XCAP::Register::CBC;
43  else if(str::iff::stringContains(s, "IDCODE"))
44  return XCAP::Register::IDCODE;
45  else if(str::iff::stringContains(s, "AXSS"))
46  return XCAP::Register::AXSS;
47  else if(str::iff::stringContains(s, "COR1"))
48  return XCAP::Register::COR1;
49  else if(str::iff::stringContains(s, "WBSTAR"))
50  return XCAP::Register::WBSTAR;
51  else if(str::iff::stringContains(s, "TIMER"))
52  return XCAP::Register::TIMER;
53  else if(str::iff::stringContains(s, "MAGIC0"))
54  return XCAP::Register::MAGIC0;
55  else if(str::iff::stringContains(s, "BOOTSTS"))
56  return XCAP::Register::BOOTSTS;
57  else if(str::iff::stringContains(s, "CTRL1"))
58  return XCAP::Register::CTRL1;
59  else if(str::iff::stringContains(s, "MAGIC1"))
60  return XCAP::Register::MAGIC1;
61  else if(str::iff::stringContains(s, "BSPI"))
62  return XCAP::Register::BSPI;
63 
64  return XCAP::Register::UNDEFINED;
65 }
66 
67 inline XCAP::Command getXCAPcommand(std::string s)
68 {
69  if(str::iff::stringContains(s, "NULL"))
70  return XCAP::Command::NULLCMD;
71  else if(str::iff::stringContains(s, "WCFG", "WRITE CONFIG"))
72  return XCAP::Command::WCFG;
73  else if(str::iff::stringContains(s, "MFW", "MULTIPLE FRAME WRITE"))
74  return XCAP::Command::MFW;
75  else if(str::iff::stringContains(s, "DGHIGH", "DEASSERT GHIGH"))
76  return XCAP::Command::DGHIGH;
77  else if(str::iff::stringContains(s, "RCFG", "READ CONFIG"))
78  return XCAP::Command::RCFG;
79  else if(str::iff::stringContains(s, "START"))
80  return XCAP::Command::START;
81  else if(str::iff::stringContains(s, "URAM", "CLEAR URAM"))
82  return XCAP::Command::URAM;
83  else if(str::iff::stringContains(s, "RCRC", "RESET CRC"))
84  return XCAP::Command::RCRC;
85  else if(str::iff::stringContains(s, "AGHIGH", "ASSERT GHIGH"))
86  return XCAP::Command::AGHIGH;
87  else if(str::iff::stringContains(s, "SWITCH"))
88  return XCAP::Command::SWITCH;
89  else if(str::iff::stringContains(s, "GRESTORE"))
90  return XCAP::Command::GRESTORE;
91  else if(str::iff::stringContains(s, "SHUTDOWN"))
92  return XCAP::Command::SHUTDOWN;
93  else if(str::iff::stringContains(s, "DESYNC"))
94  return XCAP::Command::DESYNC;
95  else if(str::iff::stringContains(s, "IPROG"))
96  return XCAP::Command::IPROG;
97  else if(str::iff::stringContains(s, "CRCC"))
98  return XCAP::Command::CRCC;
99  else if(str::iff::stringContains(s, "LTIMER"))
100  return XCAP::Command::LTIMER;
101  else if(str::iff::stringContains(s, "BSPI_READ"))
102  return XCAP::Command::BSPI_READ;
103  else if(str::iff::stringContains(s, "FALL_EDGE"))
104  return XCAP::Command::FALL_EDGE;
105  else if(str::iff::stringContains(s, "MAGIC2"))
106  return XCAP::Command::MAGIC2;
107 
108  return XCAP::Command::UNDEFINED;
109 }
110 
111 inline void writeXCAPcommandName(std::ofstream& fout, XCAP::Command commandID)
112 {
113  switch(commandID){
114  case XCAP::Command::NULLCMD:
115  fout << "Null Command";
116  break;
117  case XCAP::Command::WCFG:
118  fout << "Write Config";
119  break;
120  case XCAP::Command::MFW:
121  fout << "Multiple Frame Write";
122  break;
123  case XCAP::Command::DGHIGH:
124  fout << "Deassert GHIGH";
125  break;
126  case XCAP::Command::RCFG:
127  fout << "Read Config";
128  break;
129  case XCAP::Command::START:
130  fout << "Start";
131  break;
132  case XCAP::Command::URAM:
133  fout << "Clear URAM";
134  break;
135  case XCAP::Command::RCRC:
136  fout << "Reset CRC";
137  break;
138  case XCAP::Command::AGHIGH:
139  fout << "Assert GHIGH";
140  break;
141  case XCAP::Command::SWITCH:
142  fout << "Switch";
143  break;
144  case XCAP::Command::GRESTORE:
145  fout << "GRestore";
146  break;
147  case XCAP::Command::SHUTDOWN:
148  fout << "Shutdown";
149  break;
150  case XCAP::Command::DESYNC:
151  fout << "Desync";
152  break;
153  case XCAP::Command::IPROG:
154  fout << "IProg";
155  break;
156  case XCAP::Command::CRCC:
157  fout << "CRCC";
158  break;
159  case XCAP::Command::LTIMER:
160  fout << "LTimer";
161  break;
162  case XCAP::Command::BSPI_READ:
163  fout << "BSPI_Read";
164  break;
165  case XCAP::Command::FALL_EDGE:
166  fout << "Fall_Edge";
167  break;
168  case XCAP::Command::MAGIC2:
169  fout << "MAGIC2";
170  break;
171  default:
172  fout << std::string("UNKNOWN(").append(std::to_string(static_cast<int>(commandID))).append(")");
173  break;
174  }
175 }
176 
177 inline void writeXCAPregisterName(std::ofstream& fout, XCAP::Register registerID)
178 {
179  switch(registerID){
180  case XCAP::Register::CRC:
181  fout << "CRC";
182  break;
183  case XCAP::Register::FAR:
184  fout << "FAR";
185  break;
186  case XCAP::Register::FDRI:
187  fout << "FDRI";
188  break;
189  case XCAP::Register::FDRO:
190  fout << "FDRO";
191  break;
192  case XCAP::Register::CMD:
193  fout << "CMD";
194  break;
195  case XCAP::Register::CTRL0:
196  fout << "CTRL0";
197  break;
198  case XCAP::Register::MASK:
199  fout << "MASK";
200  break;
201  case XCAP::Register::STAT:
202  fout << "STAT";
203  break;
204  case XCAP::Register::LOUT:
205  fout << "LOUT";
206  break;
207  case XCAP::Register::COR0:
208  fout << "COR0";
209  break;
210  case XCAP::Register::MFWR:
211  fout << "MFWR";
212  break;
213  case XCAP::Register::CBC:
214  fout << "CBC";
215  break;
216  case XCAP::Register::IDCODE:
217  fout << "IDCODE";
218  break;
219  case XCAP::Register::AXSS:
220  fout << "AXSS";
221  break;
222  case XCAP::Register::COR1:
223  fout << "COR1";
224  break;
225  case XCAP::Register::WBSTAR:
226  fout << "WBSTAR";
227  break;
228  case XCAP::Register::TIMER:
229  fout << "TIMER";
230  break;
231  case XCAP::Register::MAGIC0:
232  fout << "MAGIC0";
233  break;
234  case XCAP::Register::BOOTSTS:
235  fout << "BOOTSTS";
236  break;
237  case XCAP::Register::CTRL1:
238  fout << "CTRL1";
239  break;
240  case XCAP::Register::MAGIC1:
241  fout << "MAGIC1";
242  break;
243  case XCAP::Register::BSPI:
244  fout << "BSPI";
245  break;
246  default:
247  fout << std::string("UNKNOWN(").append(std::to_string(static_cast<int>(registerID))).append(")");
248  break;
249  }
250 }
251 
253 inline uint32_t XCAP_getInstructionType(uint32_t instruction)
254 {
255  return ((instruction>>29) & 0x7); // type is @ bits [31:29]
256 }
257 
259 inline XCAP::Operation XCAP_getInstructionOperation(uint32_t instruction)
260 {
261  return static_cast<XCAP::Operation>((instruction>>27) & 0x3); //Operation is @ bits [28:27]
262 }
263 
265 inline uint32_t XCAP_getInstructionPayload(uint32_t instruction)
266 {
267  return (instruction & 0x07FFFFFF); //Payload in type 2 instructions is @ bits [26:0]
268 }
269 
271 inline XCAP::Register XCAP_getInstructionRegister(uint32_t instruction)
272 {
273  return static_cast<XCAP::Register>((instruction>>13) & 0x1F); //Register in type 1 instructions is @ bits [17:13]
274 }
275 
277 inline uint32_t XCAP_getInstructionWordCount(uint32_t instruction)
278 {
279  return (instruction & 0x7FF); //WordCount in type 1 instructions is @ bits [10:0]
280 }
281 
283 inline uint32_t XCAP_getInstruction(int type, XCAP::Operation operation, XCAP::Register reg, int payload)
284 {
285  //type 1 instr: type@[31:29] ; operation@[28:27] ; reg@[17:13] ; payload@[10:0]
286  //type 2 instr: type@[31:29] ; operation@[28:27] ; payload@[26:0]
287  //This function works for both types, but is not safe for bad instructions
288  return (((type & 0x7) << 29) | ((static_cast<int>(operation) & 0x3) << 27) | ((static_cast<int>(reg) & 0x1F) << 13) | (payload & 0x07FFFFFF));
289 }
290 
292 inline uint32_t XCAP_getType1Instruction(XCAP::Operation operation, XCAP::Register reg, int payload)
293 {
294  return XCAP_getInstruction(1, operation, reg, (payload & 0x7FF));
295 }
296 
298 inline uint32_t XCAP_getType1NopInstruction(int payload)
299 {
300  return XCAP_getType1Instruction(XCAP::Operation::NOP, static_cast<XCAP::Register>(0), payload);
301 }
302 
304 inline uint32_t XCAP_getType1ReadInstruction(XCAP::Register reg, int payload)
305 {
306  return XCAP_getType1Instruction(XCAP::Operation::READ, reg, (payload & 0x7FF));
307 }
308 
310 inline uint32_t XCAP_getType1WriteInstruction(XCAP::Register reg, int payload)
311 {
312  return XCAP_getType1Instruction(XCAP::Operation::WRITE, reg, (payload & 0x7FF));
313 }
314 
316 inline uint32_t XCAP_getType1ReservedInstruction(int payload)
317 {
318  return XCAP_getType1Instruction(XCAP::Operation::RESERVED, static_cast<XCAP::Register>(0), payload);
319 }
320 
322 inline uint32_t XCAP_getType2Instruction(XCAP::Operation operation, int payload)
323 {
324  return XCAP_getInstruction(2, operation, static_cast<XCAP::Register>(0), payload);
325 }
326 
328 inline uint32_t XCAP_getType2NopInstruction(int payload)
329 {
330  return XCAP_getType2Instruction(XCAP::Operation::NOP, payload);
331 }
332 
334 inline uint32_t XCAP_getType2ReadInstruction(int payload)
335 {
336  return XCAP_getType2Instruction(XCAP::Operation::READ, (payload & 0x07FFFFFF));
337 }
338 
340 inline uint32_t XCAP_getType2WriteInstruction(int payload)
341 {
342  return XCAP_getType2Instruction(XCAP::Operation::WRITE, (payload & 0x07FFFFFF));
343 }
344 
346 inline uint32_t XCAP_getType2ReservedInstruction(int payload)
347 {
348  return XCAP_getType2Instruction(XCAP::Operation::RESERVED, payload);
349 }
350 
352 inline void XCAP_writeNOP(std::ofstream& fout, int cnt, int payload, Endianness e)
353 {
354  uint32_t instruction = XCAP_getType1NopInstruction(payload);
355  for(int i = 0 ; i < cnt ; i++)
356  FileIO::write32(fout, instruction, e);
357 }
358 
360 inline void XCAP_writeRESERVED(std::ofstream& fout, int cnt, int payload, Endianness e)
361 {
362  uint32_t instruction = XCAP_getType1ReservedInstruction(payload);
363  for(int i = 0 ; i < cnt ; i++)
364  FileIO::write32(fout, instruction, e);
365 }
366 
368 inline void XCAP_writeSelectRegister(std::ofstream& fout, XCAP::Register reg, Endianness e)
369 {
370  uint32_t instruction = XCAP_getType1WriteInstruction(reg, 0);
371  FileIO::write32(fout, instruction, e);
372 }
373 
375 inline void XCAP_writeReadRegister(std::ofstream& fout, XCAP::Register reg, int readLength, Endianness e)
376 {
377  uint32_t instruction = XCAP_getType1ReadInstruction(reg, readLength);
378  FileIO::write32(fout, instruction, e);
379 }
380 
382 inline void XCAP_writeRegister(std::ofstream& fout, XCAP::Register reg, int writeValue, Endianness e)
383 {
384  uint32_t instruction = XCAP_getType1WriteInstruction(reg, 1);
385  FileIO::write32(fout, instruction, e);
386  FileIO::write32(fout, writeValue, e);
387 }
388 
390 inline void XCAP_writeCommand(std::ofstream& fout, XCAP::Command cmd, Endianness e)
391 {
392  XCAP_writeRegister(fout, XCAP::Register::CMD, static_cast<int>(cmd), e);
393 }
394 
396 inline void XCAP_writeMaskAndRegister(std::ofstream& fout, XCAP::Register reg, int writeMask, int writeValue, Endianness e)
397 {
398  XCAP_writeRegister(fout, XCAP::Register::MASK, writeMask, e);
399  XCAP_writeRegister(fout, reg, writeValue, e);
400 }
401 
403 inline void XCAP_writeFDRI1(std::ofstream& fout, int wordCount, Endianness e)
404 {
405  uint32_t instruction = XCAP_getType1WriteInstruction(XCAP::Register::FDRI, wordCount);
406  FileIO::write32(fout, instruction, e);
407 }
408 
410 inline void XCAP_writeType2(std::ofstream& fout, int wordCount, Endianness e)
411 {
412  uint32_t instruction = XCAP_getType2WriteInstruction(wordCount);
413  FileIO::write32(fout, instruction, e);
414 }
415 
417 inline void XCAP_writeFDRI(std::ofstream& fout, int wordCount, Endianness e)
418 {
419  XCAP_writeFDRI1(fout, 0, e);
420  XCAP_writeType2(fout, wordCount, e);
421 }
422 
424 inline uint32_t XCAP_IDCODEInstruction()
425 {
426  return XCAP_getType1WriteInstruction(XCAP::Register::IDCODE, 1);
427 }
428 
430 inline uint32_t XCAP_getSyncInstruction()
431 {
432  return FABRIC_SYNC_WORD;
433 }
434 
436 inline void XCAP_writeSYNQ(std::ofstream& fout, Endianness e)
437 {
438  FileIO::write32(fout, XCAP_getSyncInstruction(), e);
439 }
440 
441 enum class DONE_CYCLE{
442  //Start-up cycle to release the DONE pin:
443  Phase1 = 0,
444  Phase2 = 1,
445  Phase3 = 2,
446  Phase4 = 3,
447  Phase5 = 4,
448  Phase6 = 5
449 };
450 enum class MATCH_CYCLE{
451  //Start-up cycle to stall in until DCI matches:
452  Phase0 = 0,
453  Phase1 = 1,
454  Phase2 = 2,
455  Phase3 = 3,
456  Phase4 = 4,
457  Phase5 = 5,
458  Phase6 = 6,
459  NoWait = 7
460 };
461 enum class LOCK_CYCLE{
462  //Start-up cycle to stall in until MMCMs lock:
463  Phase0 = 0,
464  Phase1 = 1,
465  Phase2 = 2,
466  Phase3 = 3,
467  Phase4 = 4,
468  Phase5 = 5,
469  Phase6 = 6,
470  NoWait = 7
471 };
472 enum class GTS_CYCLE{
473  //Start-up cycle to deassert the Global 3-State (GTS) signal:
474  Phase1 = 0,
475  Phase2 = 1,
476  Phase3 = 2,
477  Phase4 = 3,
478  Phase5 = 4,
479  Phase6 = 5,
480  GTS_DONE = 6
481 };
482 enum class GWE_CYCLE{
483  //Start-up phase to deassert the Global Write Enable (GWE) signal:
484  Phase1 = 0,
485  Phase2 = 1,
486  Phase3 = 2,
487  Phase4 = 3,
488  Phase5 = 4,
489  Phase6 = 5,
490  GWE_DONE = 6
491 };
493 inline uint32_t XCAP_getCOR0value(int Reserved_31_27, int ECLK_EN, int Reserved_25, int DRIVE_DONE, int Reserved_23, int OSCFSEL, int Reserved_16_15, DONE_CYCLE selDONE_CYCLE, MATCH_CYCLE selMATCH_CYCLE, LOCK_CYCLE selLOCK_CYCLE, GTS_CYCLE selGTS_CYCLE, GWE_CYCLE selGWE_CYCLE)
494 {
495  uint32_t retValue = 0;
496  retValue |= Reserved_31_27 << 27;
497  retValue |= ECLK_EN << 26;
498  retValue |= Reserved_25 << 25;
499  retValue |= DRIVE_DONE << 24;
500  retValue |= Reserved_23 << 23;
501  retValue |= OSCFSEL << 17;
502  retValue |= Reserved_16_15 << 15;
503  retValue |= static_cast<int>(selDONE_CYCLE) << 12;
504  retValue |= static_cast<int>(selMATCH_CYCLE) << 9;
505  retValue |= static_cast<int>(selLOCK_CYCLE) << 6;
506  retValue |= static_cast<int>(selGTS_CYCLE) << 3;
507  retValue |= static_cast<int>(selGWE_CYCLE);
508  return retValue;
509 }
510 
511 
513 inline uint32_t XCAP_getCTRL0value(int EFUSE_KEY, int ICAP_SELECT, int Reserved_29_13, int OverTempShutDown, int Reserved_11, int ConfigFallback, int Reserved_9, int GLUTMASK_B, int Reserved_7, int DEC, int SBITS, int PERSIST, int Reserved_2_1, int GTS_USR_B)
514 {
515  uint32_t retValue = 0;
516  retValue |= EFUSE_KEY << 31; //Selects the AES key source: 0: Battery-backed RAM (default) 1: eFUSE
517  retValue |= ICAP_SELECT << 30; //ICAPE3 port select: 0: Top ICAPE3 port enabled (default) 1: Bottom ICAPE3 port enabled
518  retValue |= Reserved_29_13 << 13;
519  retValue |= OverTempShutDown << 12; //high-active: enables over-temperature shutdown (default:0)
520  retValue |= Reserved_11 << 11;
521  retValue |= ConfigFallback << 10; //Stops when configuration fails and disables fallback to the default bitstream. 0: Enables fallback (default)
522  retValue |= Reserved_9 << 9;
523  retValue |= GLUTMASK_B << 8; //Global LUT mask signal. Masks any changeable memory cell readback value. 0: Masks changeable memory cell readback value, such as distributed RAM or SRL 1: Does not mask changeable memory cell readback values(default)
524  retValue |= Reserved_7 << 7;
525  retValue |= DEC << 6; //AES decryptor enable bit: 0: Decryptor disabled (default) 1: Decryptor enabled
526  retValue |= SBITS << 4; //Security level. The FPGA security level is extended to encrypted bitstreams. It is applicable to the configuration port, not to ICAPE3. The security level takes affect at the end of the encrypted bitstream or after EOS for an unencrypted bitstream. 00: Read/write OK (default) 01: Readback disabled 1x: Both writes and reads disabled Only FAR and FDRI allow encrypt write access for security levels 00 and 01.
527  retValue |= PERSIST << 3; //The configuration interface defined by M2:M0 remains after configuration. Typically used only with the SelectMAP interface to allow reconfiguration and readback. See Chapter 5, SelectMAP Configuration Modes. 0: No (default) 1: Yes
528  retValue |= Reserved_2_1 << 1;
529  retValue |= GTS_USR_B; //Active-Low global 3-state I/Os. Turns off pull-ups if GTS_CFG_B is also asserted. 0: I/Os 3-stated 1: I/Os active (default)
530  return retValue;
531 }
Endianness
Endianness
< Endianness in byteman is represented not only by big/little endian, but also by potential bit swapp...
Definition: Endianness.h:47
GTS_CYCLE
GTS_CYCLE
Definition: inlineCAP.h:472
GTS_CYCLE::GTS_DONE
@ GTS_DONE
GTS tracks DONE pin. Bitstream property: GTS_CYCLE:DONE.
XCAP_getInstructionRegister
XCAP::Register XCAP_getInstructionRegister(uint32_t instruction)
Parses and returns instruction register. This is the register being addressed if the instruction is o...
Definition: inlineCAP.h:271
XCAP_getInstructionOperation
XCAP::Operation XCAP_getInstructionOperation(uint32_t instruction)
Parses and returns instruction operation. Most Xil instructions will NOP or write.
Definition: inlineCAP.h:259
XCAP_getInstructionPayload
uint32_t XCAP_getInstructionPayload(uint32_t instruction)
Parses and returns instruction payload. This is the immediate value after instruction type and operat...
Definition: inlineCAP.h:265
XCAP_writeRegister
void XCAP_writeRegister(std::ofstream &fout, XCAP::Register reg, int writeValue, Endianness e)
Generate the encoding for writing a CAP register and write it to file ofstream.
Definition: inlineCAP.h:382
MATCH_CYCLE
MATCH_CYCLE
Definition: inlineCAP.h:450
XCAP_getInstructionWordCount
uint32_t XCAP_getInstructionWordCount(uint32_t instruction)
Parses and returns instruction word count. This is the number of words to be read/written if the inst...
Definition: inlineCAP.h:277
XCAP_getSyncInstruction
uint32_t XCAP_getSyncInstruction()
Generate and return the encoding for a SYNC instruction.
Definition: inlineCAP.h:430
XCAP_writeFDRI1
void XCAP_writeFDRI1(std::ofstream &fout, int wordCount, Endianness e)
Generate and write only a type 1 FDRI command.
Definition: inlineCAP.h:403
getXCAPcommand
XCAP::Command getXCAPcommand(std::string s)
Definition: inlineCAP.h:67
XCAP_writeCommand
void XCAP_writeCommand(std::ofstream &fout, XCAP::Command cmd, Endianness e)
Generate the encoding for writing a CAP command and write it to file ofstream.
Definition: inlineCAP.h:390
XCAP_writeFDRI
void XCAP_writeFDRI(std::ofstream &fout, int wordCount, Endianness e)
Generate and write an FDRI command. Always uses type 2 command for simplicity.
Definition: inlineCAP.h:417
XCAP_getType1NopInstruction
uint32_t XCAP_getType1NopInstruction(int payload)
Generate and return the encoding for a type 1 NOP instruction.
Definition: inlineCAP.h:298
XCAP_getType1WriteInstruction
uint32_t XCAP_getType1WriteInstruction(XCAP::Register reg, int payload)
Generate and return the encoding for a type 1 Write instruction.
Definition: inlineCAP.h:310
XCAP_IDCODEInstruction
uint32_t XCAP_IDCODEInstruction()
Generate and return the encoding for a IDCODE writing instruction.
Definition: inlineCAP.h:424
XCAP_getType2WriteInstruction
uint32_t XCAP_getType2WriteInstruction(int payload)
Generate and return the encoding for a type 2 Write instruction.
Definition: inlineCAP.h:340
XCAP_writeSYNQ
void XCAP_writeSYNQ(std::ofstream &fout, Endianness e)
Generate and write an SYNQ command.
Definition: inlineCAP.h:436
DONE_CYCLE
DONE_CYCLE
Definition: inlineCAP.h:441
XCAP_getType1ReadInstruction
uint32_t XCAP_getType1ReadInstruction(XCAP::Register reg, int payload)
Generate and return the encoding for a type 1 Read instruction.
Definition: inlineCAP.h:304
FABRIC_SYNC_WORD
#define FABRIC_SYNC_WORD
Definition: inlineCAP.h:17
XCAP_writeSelectRegister
void XCAP_writeSelectRegister(std::ofstream &fout, XCAP::Register reg, Endianness e)
Generate the encoding for "selecting" a CAP register and write it to file ofstream.
Definition: inlineCAP.h:368
XCAP_writeRESERVED
void XCAP_writeRESERVED(std::ofstream &fout, int cnt, int payload, Endianness e)
Generate the encoding for Reserved instructions and write them to file ofstream.
Definition: inlineCAP.h:360
XCAP_getType1ReservedInstruction
uint32_t XCAP_getType1ReservedInstruction(int payload)
Generate and return the encoding for a type 1 Reserved instruction.
Definition: inlineCAP.h:316
XCAP_writeType2
void XCAP_writeType2(std::ofstream &fout, int wordCount, Endianness e)
Generate and write only a type 2 FDRI command.
Definition: inlineCAP.h:410
XCAP_writeMaskAndRegister
void XCAP_writeMaskAndRegister(std::ofstream &fout, XCAP::Register reg, int writeMask, int writeValue, Endianness e)
Generate the encoding for writing a CAP register with a mask and write it to file ofstream.
Definition: inlineCAP.h:396
XCAP_getType2NopInstruction
uint32_t XCAP_getType2NopInstruction(int payload)
Generate and return the encoding for a type 2 NOP instruction.
Definition: inlineCAP.h:328
XCAP_getType2Instruction
uint32_t XCAP_getType2Instruction(XCAP::Operation operation, int payload)
Generate and return the encoding for a type 2 instruction.
Definition: inlineCAP.h:322
XCAP_getInstructionType
uint32_t XCAP_getInstructionType(uint32_t instruction)
Parses and returns instruction type. Valid Xil instructions will be of types 1 and 2.
Definition: inlineCAP.h:253
XCAP_getType1Instruction
uint32_t XCAP_getType1Instruction(XCAP::Operation operation, XCAP::Register reg, int payload)
Generate and return the encoding for a type 1 instruction.
Definition: inlineCAP.h:292
writeXCAPcommandName
void writeXCAPcommandName(std::ofstream &fout, XCAP::Command commandID)
Definition: inlineCAP.h:111
XCAP_getType2ReadInstruction
uint32_t XCAP_getType2ReadInstruction(int payload)
Generate and return the encoding for a type 2 Read instruction.
Definition: inlineCAP.h:334
GWE_CYCLE
GWE_CYCLE
Definition: inlineCAP.h:482
GWE_CYCLE::GWE_DONE
@ GWE_DONE
GWE tracks DONE pin. Bitstream property: GWE_CYCLE:DONE.
XCAP_getType2ReservedInstruction
uint32_t XCAP_getType2ReservedInstruction(int payload)
Generate and return the encoding for a type 2 Reserved instruction.
Definition: inlineCAP.h:346
XCAP_getCOR0value
uint32_t XCAP_getCOR0value(int Reserved_31_27, int ECLK_EN, int Reserved_25, int DRIVE_DONE, int Reserved_23, int OSCFSEL, int Reserved_16_15, DONE_CYCLE selDONE_CYCLE, MATCH_CYCLE selMATCH_CYCLE, LOCK_CYCLE selLOCK_CYCLE, GTS_CYCLE selGTS_CYCLE, GWE_CYCLE selGWE_CYCLE)
Generate COR0 register write value.
Definition: inlineCAP.h:493
writeXCAPregisterName
void writeXCAPregisterName(std::ofstream &fout, XCAP::Register registerID)
Definition: inlineCAP.h:177
XCAP_writeNOP
void XCAP_writeNOP(std::ofstream &fout, int cnt, int payload, Endianness e)
Generate the encoding for NOP instructions and write them to file ofstream.
Definition: inlineCAP.h:352
XCAP_getCTRL0value
uint32_t XCAP_getCTRL0value(int EFUSE_KEY, int ICAP_SELECT, int Reserved_29_13, int OverTempShutDown, int Reserved_11, int ConfigFallback, int Reserved_9, int GLUTMASK_B, int Reserved_7, int DEC, int SBITS, int PERSIST, int Reserved_2_1, int GTS_USR_B)
Generate CTRL0 register write value.
Definition: inlineCAP.h:513
XCAP_writeReadRegister
void XCAP_writeReadRegister(std::ofstream &fout, XCAP::Register reg, int readLength, Endianness e)
Generate the encoding for reading a CAP register and write it to file ofstream.
Definition: inlineCAP.h:375
getXCAPregister
XCAP::Register getXCAPregister(std::string s)
Definition: inlineCAP.h:19
LOCK_CYCLE
LOCK_CYCLE
Definition: inlineCAP.h:461
XCAP_getInstruction
uint32_t XCAP_getInstruction(int type, XCAP::Operation operation, XCAP::Register reg, int payload)
Generate and return the encoding for an instruction.
Definition: inlineCAP.h:283
Endian::to_string
std::string to_string(Endianness e)
Definition: Endianness.h:56
FileIO::write32
void write32(std::ofstream &fout, uint32_t writeValue, Endianness e=Endianness::NATIVE)
Definition: FileIO.h:419
XCAP::Operation
Operation
Definition: XCAP.h:69
XCAP::Register
Register
Definition: XCAP.h:20
XCAP::Command
Command
Definition: XCAP.h:46
str::iff::stringContains
bool stringContains(std::string checkedString)
Returns false. End of recursion for template.
Definition: iff.h:57
Generated on Tue Nov 29 2022 12:57:36 for byteman by doxygen 1.9.1