inlineCAP.h File Reference

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Macros
#define	FABRIC_SYNC_WORD   0xAA995566

Enumerations
enum class	DONE_CYCLE {   Phase1 = 0 , Phase2 = 1 , Phase3 = 2 , Phase4 = 3 ,   Phase5 = 4 , Phase6 = 5 }
enum class	GTS_CYCLE {   Phase1 = 0 , Phase2 = 1 , Phase3 = 2 , Phase4 = 3 ,   Phase5 = 4 , Phase6 = 5 , GTS_DONE = 6 }
enum class	GWE_CYCLE {   Phase1 = 0 , Phase2 = 1 , Phase3 = 2 , Phase4 = 3 ,   Phase5 = 4 , Phase6 = 5 , GWE_DONE = 6 }
enum class	LOCK_CYCLE {   Phase0 = 0 , Phase1 = 1 , Phase2 = 2 , Phase3 = 3 ,   Phase4 = 4 , Phase5 = 5 , Phase6 = 6 , NoWait = 7 }
enum class	MATCH_CYCLE {   Phase0 = 0 , Phase1 = 1 , Phase2 = 2 , Phase3 = 3 ,   Phase4 = 4 , Phase5 = 5 , Phase6 = 6 , NoWait = 7 }

Functions
XCAP::Command	getXCAPcommand (std::string s)
XCAP::Register	getXCAPregister (std::string s)
void	writeXCAPcommandName (std::ofstream &fout, XCAP::Command commandID)
void	writeXCAPregisterName (std::ofstream &fout, XCAP::Register registerID)
uint32_t	XCAP_getCOR0value (int Reserved_31_27, int ECLK_EN, int Reserved_25, int DRIVE_DONE, int Reserved_23, int OSCFSEL, int Reserved_16_15, DONE_CYCLE selDONE_CYCLE, MATCH_CYCLE selMATCH_CYCLE, LOCK_CYCLE selLOCK_CYCLE, GTS_CYCLE selGTS_CYCLE, GWE_CYCLE selGWE_CYCLE)
	Generate COR0 register write value. More...
uint32_t	XCAP_getCTRL0value (int EFUSE_KEY, int ICAP_SELECT, int Reserved_29_13, int OverTempShutDown, int Reserved_11, int ConfigFallback, int Reserved_9, int GLUTMASK_B, int Reserved_7, int DEC, int SBITS, int PERSIST, int Reserved_2_1, int GTS_USR_B)
	Generate CTRL0 register write value. More...
uint32_t	XCAP_getInstruction (int type, XCAP::Operation operation, XCAP::Register reg, int payload)
	Generate and return the encoding for an instruction. More...
XCAP::Operation	XCAP_getInstructionOperation (uint32_t instruction)
	Parses and returns instruction operation. Most Xil instructions will NOP or write. More...
uint32_t	XCAP_getInstructionPayload (uint32_t instruction)
	Parses and returns instruction payload. This is the immediate value after instruction type and operation encodings. More...
XCAP::Register	XCAP_getInstructionRegister (uint32_t instruction)
	Parses and returns instruction register. This is the register being addressed if the instruction is of type 1. More...
uint32_t	XCAP_getInstructionType (uint32_t instruction)
	Parses and returns instruction type. Valid Xil instructions will be of types 1 and 2. More...
uint32_t	XCAP_getInstructionWordCount (uint32_t instruction)
	Parses and returns instruction word count. This is the number of words to be read/written if the instruction is of type 1. More...
uint32_t	XCAP_getSyncInstruction ()
	Generate and return the encoding for a SYNC instruction. More...
uint32_t	XCAP_getType1Instruction (XCAP::Operation operation, XCAP::Register reg, int payload)
	Generate and return the encoding for a type 1 instruction. More...
uint32_t	XCAP_getType1NopInstruction (int payload)
	Generate and return the encoding for a type 1 NOP instruction. More...
uint32_t	XCAP_getType1ReadInstruction (XCAP::Register reg, int payload)
	Generate and return the encoding for a type 1 Read instruction. More...
uint32_t	XCAP_getType1ReservedInstruction (int payload)
	Generate and return the encoding for a type 1 Reserved instruction. More...
uint32_t	XCAP_getType1WriteInstruction (XCAP::Register reg, int payload)
	Generate and return the encoding for a type 1 Write instruction. More...
uint32_t	XCAP_getType2Instruction (XCAP::Operation operation, int payload)
	Generate and return the encoding for a type 2 instruction. More...
uint32_t	XCAP_getType2NopInstruction (int payload)
	Generate and return the encoding for a type 2 NOP instruction. More...
uint32_t	XCAP_getType2ReadInstruction (int payload)
	Generate and return the encoding for a type 2 Read instruction. More...
uint32_t	XCAP_getType2ReservedInstruction (int payload)
	Generate and return the encoding for a type 2 Reserved instruction. More...
uint32_t	XCAP_getType2WriteInstruction (int payload)
	Generate and return the encoding for a type 2 Write instruction. More...
uint32_t	XCAP_IDCODEInstruction ()
	Generate and return the encoding for a IDCODE writing instruction. More...
void	XCAP_writeCommand (std::ofstream &fout, XCAP::Command cmd, Endianness e)
	Generate the encoding for writing a CAP command and write it to file ofstream. More...
void	XCAP_writeFDRI (std::ofstream &fout, int wordCount, Endianness e)
	Generate and write an FDRI command. Always uses type 2 command for simplicity. More...
void	XCAP_writeFDRI1 (std::ofstream &fout, int wordCount, Endianness e)
	Generate and write only a type 1 FDRI command. More...
void	XCAP_writeMaskAndRegister (std::ofstream &fout, XCAP::Register reg, int writeMask, int writeValue, Endianness e)
	Generate the encoding for writing a CAP register with a mask and write it to file ofstream. More...
void	XCAP_writeNOP (std::ofstream &fout, int cnt, int payload, Endianness e)
	Generate the encoding for NOP instructions and write them to file ofstream. More...
void	XCAP_writeReadRegister (std::ofstream &fout, XCAP::Register reg, int readLength, Endianness e)
	Generate the encoding for reading a CAP register and write it to file ofstream. More...
void	XCAP_writeRegister (std::ofstream &fout, XCAP::Register reg, int writeValue, Endianness e)
	Generate the encoding for writing a CAP register and write it to file ofstream. More...
void	XCAP_writeRESERVED (std::ofstream &fout, int cnt, int payload, Endianness e)
	Generate the encoding for Reserved instructions and write them to file ofstream. More...
void	XCAP_writeSelectRegister (std::ofstream &fout, XCAP::Register reg, Endianness e)
	Generate the encoding for "selecting" a CAP register and write it to file ofstream. More...
void	XCAP_writeSYNQ (std::ofstream &fout, Endianness e)
	Generate and write an SYNQ command. More...
void	XCAP_writeType2 (std::ofstream &fout, int wordCount, Endianness e)
	Generate and write only a type 2 FDRI command. More...

Macro Definition Documentation

FABRIC_SYNC_WORD

#define FABRIC_SYNC_WORD   0xAA995566

Definition at line 17 of file inlineCAP.h.

Enumeration Type Documentation

DONE_CYCLE

enum DONE_CYCLE

strong

Enumerator
Phase1
Phase2
Phase3
Phase4
Phase5
Phase6

Definition at line 441 of file inlineCAP.h.

                     {
    //Start-up cycle to release the DONE pin:
    Phase1 = 0,
    Phase2 = 1,
    Phase3 = 2,
    Phase4 = 3,
    Phase5 = 4,
    Phase6 = 5
};

GTS_CYCLE

enum GTS_CYCLE

strong

Enumerator
Phase1
Phase2
Phase3
Phase4
Phase5
Phase6
GTS_DONE	GTS tracks DONE pin. Bitstream property: GTS_CYCLE:DONE.

Definition at line 472 of file inlineCAP.h.

                    {
    //Start-up cycle to deassert the Global 3-State (GTS) signal:
    Phase1 = 0,
    Phase2 = 1,
    Phase3 = 2,
    Phase4 = 3,
    Phase5 = 4,
    Phase6 = 5,
    GTS_DONE = 6 
};

GWE_CYCLE

enum GWE_CYCLE

strong

Enumerator
Phase1
Phase2
Phase3
Phase4
Phase5
Phase6
GWE_DONE	GWE tracks DONE pin. Bitstream property: GWE_CYCLE:DONE.

Definition at line 482 of file inlineCAP.h.

                    {
    //Start-up phase to deassert the Global Write Enable (GWE) signal:
    Phase1 = 0,
    Phase2 = 1,
    Phase3 = 2,
    Phase4 = 3,
    Phase5 = 4,
    Phase6 = 5,
    GWE_DONE = 6 
};

LOCK_CYCLE

enum LOCK_CYCLE

strong

Enumerator
Phase0
Phase1
Phase2
Phase3
Phase4
Phase5
Phase6
NoWait

Definition at line 461 of file inlineCAP.h.

                     {
    //Start-up cycle to stall in until MMCMs lock:
    Phase0 = 0,
    Phase1 = 1,
    Phase2 = 2,
    Phase3 = 3,
    Phase4 = 4,
    Phase5 = 5,
    Phase6 = 6,
    NoWait = 7
};

MATCH_CYCLE

enum MATCH_CYCLE

strong

Enumerator
Phase0
Phase1
Phase2
Phase3
Phase4
Phase5
Phase6
NoWait

Definition at line 450 of file inlineCAP.h.

                      {
    //Start-up cycle to stall in until DCI matches:
    Phase0 = 0,
    Phase1 = 1,
    Phase2 = 2,
    Phase3 = 3,
    Phase4 = 4,
    Phase5 = 5,
    Phase6 = 6,
    NoWait = 7
};

Function Documentation

getXCAPcommand()

XCAP::Command getXCAPcommand ( std::string  s )

inline

Definition at line 67 of file inlineCAP.h.

{
    if(str::iff::stringContains(s, "NULL"))
        return XCAP::Command::NULLCMD;
    else if(str::iff::stringContains(s, "WCFG", "WRITE CONFIG"))
        return XCAP::Command::WCFG;
    else if(str::iff::stringContains(s, "MFW", "MULTIPLE FRAME WRITE"))
        return XCAP::Command::MFW;
    else if(str::iff::stringContains(s, "DGHIGH", "DEASSERT GHIGH"))
        return XCAP::Command::DGHIGH;
    else if(str::iff::stringContains(s, "RCFG", "READ CONFIG"))
        return XCAP::Command::RCFG;
    else if(str::iff::stringContains(s, "START"))
        return XCAP::Command::START;
    else if(str::iff::stringContains(s, "URAM", "CLEAR URAM"))
        return XCAP::Command::URAM;
    else if(str::iff::stringContains(s, "RCRC", "RESET CRC"))
        return XCAP::Command::RCRC;
    else if(str::iff::stringContains(s, "AGHIGH", "ASSERT GHIGH"))
        return XCAP::Command::AGHIGH;
    else if(str::iff::stringContains(s, "SWITCH"))
        return XCAP::Command::SWITCH;
    else if(str::iff::stringContains(s, "GRESTORE"))
        return XCAP::Command::GRESTORE;
    else if(str::iff::stringContains(s, "SHUTDOWN"))
        return XCAP::Command::SHUTDOWN;
    else if(str::iff::stringContains(s, "DESYNC"))
        return XCAP::Command::DESYNC;
    else if(str::iff::stringContains(s, "IPROG"))
        return XCAP::Command::IPROG;
    else if(str::iff::stringContains(s, "CRCC"))
        return XCAP::Command::CRCC;
    else if(str::iff::stringContains(s, "LTIMER"))
        return XCAP::Command::LTIMER;
    else if(str::iff::stringContains(s, "BSPI_READ"))
        return XCAP::Command::BSPI_READ;
    else if(str::iff::stringContains(s, "FALL_EDGE"))
        return XCAP::Command::FALL_EDGE;
    else if(str::iff::stringContains(s, "MAGIC2"))
        return XCAP::Command::MAGIC2;
 
    return XCAP::Command::UNDEFINED;
}

References XCAP::AGHIGH, XCAP::BSPI_READ, XCAP::CRCC, XCAP::DESYNC, XCAP::DGHIGH, XCAP::FALL_EDGE, XCAP::GRESTORE, XCAP::IPROG, XCAP::LTIMER, XCAP::MAGIC2, XCAP::MFW, XCAP::NULLCMD, XCAP::RCFG, XCAP::RCRC, XCAP::SHUTDOWN, XCAP::START, str::iff::stringContains(), XCAP::SWITCH, XCAP::UNDEFINED, XCAP::URAM, and XCAP::WCFG.

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), and XilinxUltraScalePlus::assemblerAsmTo().

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getXCAPregister()

XCAP::Register getXCAPregister ( std::string  s )

inline

Definition at line 19 of file inlineCAP.h.

{
    if(str::iff::stringContains(s, "CRC"))
        return XCAP::Register::CRC;
    else if(str::iff::stringContains(s, "FAR"))
        return XCAP::Register::FAR;
    else if(str::iff::stringContains(s, "FDRI"))
        return XCAP::Register::FDRI;
    else if(str::iff::stringContains(s, "FDRO"))
        return XCAP::Register::FDRO;
    else if(str::iff::stringContains(s, "CTRL0"))
        return XCAP::Register::CTRL0;
    else if(str::iff::stringContains(s, "MASK"))
        return XCAP::Register::MASK;
    else if(str::iff::stringContains(s, "STAT"))
        return XCAP::Register::STAT;
    else if(str::iff::stringContains(s, "LOUT"))
        return XCAP::Register::LOUT;
    else if(str::iff::stringContains(s, "COR0"))
        return XCAP::Register::COR0;
    else if(str::iff::stringContains(s, "MFWR"))
        return XCAP::Register::MFWR;
    else if(str::iff::stringContains(s, "CBC"))
        return XCAP::Register::CBC;
    else if(str::iff::stringContains(s, "IDCODE"))
        return XCAP::Register::IDCODE;
    else if(str::iff::stringContains(s, "AXSS"))
        return XCAP::Register::AXSS;
    else if(str::iff::stringContains(s, "COR1"))
        return XCAP::Register::COR1;
    else if(str::iff::stringContains(s, "WBSTAR"))
        return XCAP::Register::WBSTAR;
    else if(str::iff::stringContains(s, "TIMER"))
        return XCAP::Register::TIMER;
    else if(str::iff::stringContains(s, "MAGIC0"))
        return XCAP::Register::MAGIC0;
    else if(str::iff::stringContains(s, "BOOTSTS"))
        return XCAP::Register::BOOTSTS;
    else if(str::iff::stringContains(s, "CTRL1"))
        return XCAP::Register::CTRL1;
    else if(str::iff::stringContains(s, "MAGIC1"))
        return XCAP::Register::MAGIC1;
    else if(str::iff::stringContains(s, "BSPI"))
        return XCAP::Register::BSPI;
 
    return XCAP::Register::UNDEFINED;
}

References XCAP::AXSS, XCAP::BOOTSTS, XCAP::BSPI, XCAP::CBC, XCAP::COR0, XCAP::COR1, XCAP::CRC, XCAP::CTRL0, XCAP::CTRL1, XCAP::FAR, XCAP::FDRI, XCAP::FDRO, XCAP::IDCODE, XCAP::LOUT, XCAP::MAGIC0, XCAP::MAGIC1, XCAP::MASK, XCAP::MFWR, XCAP::STAT, str::iff::stringContains(), XCAP::TIMER, XCAP::UNDEFINED, and XCAP::WBSTAR.

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), and XilinxUltraScalePlus::assemblerAsmTo().

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writeXCAPcommandName()

void writeXCAPcommandName ( std::ofstream &  fout, XCAP::Command  commandID  )

inline

Definition at line 111 of file inlineCAP.h.

{
    switch(commandID){
        case XCAP::Command::NULLCMD:
            fout << "Null Command";
            break;
        case XCAP::Command::WCFG:
            fout << "Write Config";
            break;
        case XCAP::Command::MFW:
            fout << "Multiple Frame Write";
            break;
        case XCAP::Command::DGHIGH:
            fout << "Deassert GHIGH";
            break;
        case XCAP::Command::RCFG:
            fout << "Read Config";
            break;
        case XCAP::Command::START:
            fout << "Start";
            break;
        case XCAP::Command::URAM:
            fout << "Clear URAM";
            break;
        case XCAP::Command::RCRC:
            fout << "Reset CRC";
            break;
        case XCAP::Command::AGHIGH:
            fout << "Assert GHIGH";
            break;
        case XCAP::Command::SWITCH:
            fout << "Switch";
            break;
        case XCAP::Command::GRESTORE:
            fout << "GRestore";
            break;
        case XCAP::Command::SHUTDOWN:
            fout << "Shutdown";
            break;
        case XCAP::Command::DESYNC:
            fout << "Desync";
            break;
        case XCAP::Command::IPROG:
            fout << "IProg";
            break;
        case XCAP::Command::CRCC:
            fout << "CRCC";
            break;
        case XCAP::Command::LTIMER:
            fout << "LTimer";
            break;
        case XCAP::Command::BSPI_READ:
            fout << "BSPI_Read";
            break;
        case XCAP::Command::FALL_EDGE:
            fout << "Fall_Edge";
            break;
        case XCAP::Command::MAGIC2:
            fout << "MAGIC2";
            break;
        default:
            fout << std::string("UNKNOWN(").append(std::to_string(static_cast<int>(commandID))).append(")");
            break;
    }
}

References XCAP::AGHIGH, XCAP::BSPI_READ, XCAP::CRCC, XCAP::DESYNC, XCAP::DGHIGH, XCAP::FALL_EDGE, XCAP::GRESTORE, XCAP::IPROG, XCAP::LTIMER, XCAP::MAGIC2, XCAP::MFW, XCAP::NULLCMD, XCAP::RCFG, XCAP::RCRC, XCAP::SHUTDOWN, XCAP::START, XCAP::SWITCH, Endian::to_string(), XCAP::URAM, and XCAP::WCFG.

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), and XilinxUltraScalePlus::disassemblerToAsm().

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writeXCAPregisterName()

void writeXCAPregisterName ( std::ofstream &  fout, XCAP::Register  registerID  )

inline

Definition at line 177 of file inlineCAP.h.

{
    switch(registerID){
        case XCAP::Register::CRC:
            fout << "CRC";
            break;
        case XCAP::Register::FAR:
            fout << "FAR";
            break;
        case XCAP::Register::FDRI:
            fout << "FDRI";
            break;
        case XCAP::Register::FDRO:
            fout << "FDRO";
            break;
        case XCAP::Register::CMD:
            fout << "CMD";
            break;
        case XCAP::Register::CTRL0:
            fout << "CTRL0";
            break;
        case XCAP::Register::MASK:
            fout << "MASK";
            break;
        case XCAP::Register::STAT:
            fout << "STAT";
            break;
        case XCAP::Register::LOUT:
            fout << "LOUT";
            break;
        case XCAP::Register::COR0:
            fout << "COR0";
            break;
        case XCAP::Register::MFWR:
            fout << "MFWR";
            break;
        case XCAP::Register::CBC:
            fout << "CBC";
            break;
        case XCAP::Register::IDCODE:
            fout << "IDCODE";
            break;
        case XCAP::Register::AXSS:
            fout << "AXSS";
            break;
        case XCAP::Register::COR1:
            fout << "COR1";
            break;
        case XCAP::Register::WBSTAR:
            fout << "WBSTAR";
            break;
        case XCAP::Register::TIMER:
            fout << "TIMER";
            break;
        case XCAP::Register::MAGIC0:
            fout << "MAGIC0";
            break;
        case XCAP::Register::BOOTSTS:
            fout << "BOOTSTS";
            break;
        case XCAP::Register::CTRL1:
            fout << "CTRL1";
            break;
        case XCAP::Register::MAGIC1:
            fout << "MAGIC1";
            break;
        case XCAP::Register::BSPI:
            fout << "BSPI";
            break;
        default:
            fout << std::string("UNKNOWN(").append(std::to_string(static_cast<int>(registerID))).append(")");
            break;
    }
}

References XCAP::AXSS, XCAP::BOOTSTS, XCAP::BSPI, XCAP::CBC, XCAP::CMD, XCAP::COR0, XCAP::COR1, XCAP::CRC, XCAP::CTRL0, XCAP::CTRL1, XCAP::FAR, XCAP::FDRI, XCAP::FDRO, XCAP::IDCODE, XCAP::LOUT, XCAP::MAGIC0, XCAP::MAGIC1, XCAP::MASK, XCAP::MFWR, XCAP::STAT, XCAP::TIMER, Endian::to_string(), and XCAP::WBSTAR.

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), and XilinxUltraScalePlus::disassemblerToAsm().

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XCAP_getCOR0value()

uint32_t XCAP_getCOR0value ( int  Reserved_31_27, int  ECLK_EN, int  Reserved_25, int  DRIVE_DONE, int  Reserved_23, int  OSCFSEL, int  Reserved_16_15, DONE_CYCLE  selDONE_CYCLE, MATCH_CYCLE  selMATCH_CYCLE, LOCK_CYCLE  selLOCK_CYCLE, GTS_CYCLE  selGTS_CYCLE, GWE_CYCLE  selGWE_CYCLE  )

inline

Generate COR0 register write value.

Definition at line 493 of file inlineCAP.h.

{
    uint32_t retValue = 0;
    retValue |= Reserved_31_27 << 27;
    retValue |= ECLK_EN << 26;
    retValue |= Reserved_25 << 25;
    retValue |= DRIVE_DONE << 24;
    retValue |= Reserved_23 << 23;
    retValue |= OSCFSEL << 17;
    retValue |= Reserved_16_15 << 15;
    retValue |= static_cast<int>(selDONE_CYCLE) << 12;
    retValue |= static_cast<int>(selMATCH_CYCLE) << 9;
    retValue |= static_cast<int>(selLOCK_CYCLE) << 6;
    retValue |= static_cast<int>(selGTS_CYCLE) << 3;
    retValue |= static_cast<int>(selGWE_CYCLE);
    return retValue;
}

Referenced by XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), and XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence().

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XCAP_getCTRL0value()

uint32_t XCAP_getCTRL0value ( int  EFUSE_KEY, int  ICAP_SELECT, int  Reserved_29_13, int  OverTempShutDown, int  Reserved_11, int  ConfigFallback, int  Reserved_9, int  GLUTMASK_B, int  Reserved_7, int  DEC, int  SBITS, int  PERSIST, int  Reserved_2_1, int  GTS_USR_B  )

inline

Generate CTRL0 register write value.

Definition at line 513 of file inlineCAP.h.

{
    uint32_t retValue = 0;
    retValue |= EFUSE_KEY << 31; //Selects the AES key source: 0: Battery-backed RAM (default) 1: eFUSE
    retValue |= ICAP_SELECT << 30; //ICAPE3 port select: 0: Top ICAPE3 port enabled (default) 1: Bottom ICAPE3 port enabled
    retValue |= Reserved_29_13 << 13;
    retValue |= OverTempShutDown << 12; //high-active: enables over-temperature shutdown (default:0)
    retValue |= Reserved_11 << 11;
    retValue |= ConfigFallback << 10; //Stops when configuration fails and disables fallback to the default bitstream. 0: Enables fallback (default)
    retValue |= Reserved_9 << 9;
    retValue |= GLUTMASK_B << 8; //Global LUT mask signal. Masks any changeable memory cell readback value. 0: Masks changeable memory cell readback value, such as distributed RAM or SRL 1: Does not mask changeable memory cell readback values(default)
    retValue |= Reserved_7 << 7;
    retValue |= DEC << 6; //AES decryptor enable bit: 0: Decryptor disabled (default) 1: Decryptor enabled
    retValue |= SBITS << 4; //Security level. The FPGA security level is extended to encrypted bitstreams. It is applicable to the configuration port, not to ICAPE3. The security level takes affect at the end of the encrypted bitstream or after EOS for an unencrypted bitstream. 00: Read/write OK (default) 01: Readback disabled 1x: Both writes and reads disabled Only FAR and FDRI allow encrypt write access for security levels 00 and 01.
    retValue |= PERSIST << 3; //The configuration interface defined by M2:M0 remains after configuration. Typically used only with the SelectMAP interface to allow reconfiguration and readback. See Chapter 5, SelectMAP Configuration Modes. 0: No (default) 1: Yes
    retValue |= Reserved_2_1 << 1;
    retValue |= GTS_USR_B; //Active-Low global 3-state I/Os. Turns off pull-ups if GTS_CFG_B is also asserted. 0: I/Os 3-stated 1: I/Os active (default)
    return retValue;
}

Referenced by XilinxSeries7::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRFooterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence(), and XilinxUltraScalePlus::outputBitstreamSLRHeaderBitstreamSequence().

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XCAP_getInstruction()

uint32_t XCAP_getInstruction ( int  type, XCAP::Operation  operation, XCAP::Register  reg, int  payload  )

inline

Generate and return the encoding for an instruction.

Definition at line 283 of file inlineCAP.h.

{
    //type 1 instr: type@[31:29] ; operation@[28:27] ; reg@[17:13] ; payload@[10:0]
    //type 2 instr: type@[31:29] ; operation@[28:27] ; payload@[26:0]
    //This function works for both types, but is not safe for bad instructions
    return (((type & 0x7) << 29) | ((static_cast<int>(operation) & 0x3) << 27) | ((static_cast<int>(reg) & 0x1F) << 13) | (payload & 0x07FFFFFF));
}

Referenced by XCAP_getType1Instruction(), and XCAP_getType2Instruction().

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XCAP_getInstructionOperation()

XCAP::Operation XCAP_getInstructionOperation ( uint32_t  instruction )

inline

Parses and returns instruction operation. Most Xil instructions will NOP or write.

Definition at line 259 of file inlineCAP.h.

{
    return static_cast<XCAP::Operation>((instruction>>27) & 0x3); //Operation is @ bits [28:27]
}

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), XilinxUltraScalePlus::disassemblerToAsm(), and readBitstreamMain().

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XCAP_getInstructionPayload()

uint32_t XCAP_getInstructionPayload ( uint32_t  instruction )

inline

Parses and returns instruction payload. This is the immediate value after instruction type and operation encodings.

Definition at line 265 of file inlineCAP.h.

{
    return (instruction & 0x07FFFFFF);  //Payload in type 2 instructions is @ bits [26:0]
}

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), XilinxUltraScalePlus::disassemblerToAsm(), and readBitstreamMain().

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XCAP_getInstructionRegister()

XCAP::Register XCAP_getInstructionRegister ( uint32_t  instruction )

inline

Parses and returns instruction register. This is the register being addressed if the instruction is of type 1.

Definition at line 271 of file inlineCAP.h.

{
    return static_cast<XCAP::Register>((instruction>>13) & 0x1F);   //Register in type 1 instructions is @ bits [17:13]
}

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), XilinxUltraScalePlus::disassemblerToAsm(), and readBitstreamMain().

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XCAP_getInstructionType()

uint32_t XCAP_getInstructionType ( uint32_t  instruction )

inline

Parses and returns instruction type. Valid Xil instructions will be of types 1 and 2.

Definition at line 253 of file inlineCAP.h.

{
    return ((instruction>>29) & 0x7); // type is @ bits [31:29]
}

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), XilinxUltraScalePlus::disassemblerToAsm(), and readBitstreamMain().

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XCAP_getInstructionWordCount()

uint32_t XCAP_getInstructionWordCount ( uint32_t  instruction )

inline

Parses and returns instruction word count. This is the number of words to be read/written if the instruction is of type 1.

Definition at line 277 of file inlineCAP.h.

{
    return (instruction & 0x7FF);   //WordCount in type 1 instructions is @ bits [10:0]
}

Referenced by XilinxSeries7::disassemblerToAsm(), XilinxUltraScale::disassemblerToAsm(), XilinxUltraScalePlus::disassemblerToAsm(), and readBitstreamMain().

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XCAP_getSyncInstruction()

uint32_t XCAP_getSyncInstruction ( )

inline

Generate and return the encoding for a SYNC instruction.

Definition at line 430 of file inlineCAP.h.

{
    return FABRIC_SYNC_WORD;
}

References FABRIC_SYNC_WORD.

Referenced by findBitstreamSyncSequence(), findBitstreamSyncWord(), outputCAPheaderConstant(), parseBitstreamEndianness(), and XCAP_writeSYNQ().

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XCAP_getType1Instruction()

uint32_t XCAP_getType1Instruction ( XCAP::Operation  operation, XCAP::Register  reg, int  payload  )

inline

Generate and return the encoding for a type 1 instruction.

Definition at line 292 of file inlineCAP.h.

{
    return XCAP_getInstruction(1, operation, reg, (payload & 0x7FF));
}

References XCAP_getInstruction().

Referenced by XCAP_getType1NopInstruction(), XCAP_getType1ReadInstruction(), XCAP_getType1ReservedInstruction(), and XCAP_getType1WriteInstruction().

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XCAP_getType1NopInstruction()

uint32_t XCAP_getType1NopInstruction ( int  payload )

inline

Generate and return the encoding for a type 1 NOP instruction.

Definition at line 298 of file inlineCAP.h.

{
    return XCAP_getType1Instruction(XCAP::Operation::NOP, static_cast<XCAP::Register>(0), payload);
}

References XCAP::NOP, and XCAP_getType1Instruction().

Referenced by XCAP_writeNOP().

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XCAP_getType1ReadInstruction()

uint32_t XCAP_getType1ReadInstruction ( XCAP::Register  reg, int  payload  )

inline

Generate and return the encoding for a type 1 Read instruction.

Definition at line 304 of file inlineCAP.h.

{
    return XCAP_getType1Instruction(XCAP::Operation::READ, reg, (payload & 0x7FF));
}

References XCAP::READ, and XCAP_getType1Instruction().

Referenced by XCAP_writeReadRegister().

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XCAP_getType1ReservedInstruction()

uint32_t XCAP_getType1ReservedInstruction ( int  payload )

inline

Generate and return the encoding for a type 1 Reserved instruction.

Definition at line 316 of file inlineCAP.h.

{
    return XCAP_getType1Instruction(XCAP::Operation::RESERVED, static_cast<XCAP::Register>(0), payload);
}

References XCAP::RESERVED, and XCAP_getType1Instruction().

Referenced by XCAP_writeRESERVED().

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XCAP_getType1WriteInstruction()

uint32_t XCAP_getType1WriteInstruction ( XCAP::Register  reg, int  payload  )

inline

Generate and return the encoding for a type 1 Write instruction.

Definition at line 310 of file inlineCAP.h.

{
    return XCAP_getType1Instruction(XCAP::Operation::WRITE, reg, (payload & 0x7FF));
}

References XCAP::WRITE, and XCAP_getType1Instruction().

Referenced by XCAP_IDCODEInstruction(), XCAP_writeFDRI1(), XCAP_writeRegister(), and XCAP_writeSelectRegister().

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XCAP_getType2Instruction()

uint32_t XCAP_getType2Instruction ( XCAP::Operation  operation, int  payload  )

inline

Generate and return the encoding for a type 2 instruction.

Definition at line 322 of file inlineCAP.h.

{
    return XCAP_getInstruction(2, operation, static_cast<XCAP::Register>(0), payload);
}

References XCAP_getInstruction().

Referenced by XCAP_getType2NopInstruction(), XCAP_getType2ReadInstruction(), XCAP_getType2ReservedInstruction(), and XCAP_getType2WriteInstruction().

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XCAP_getType2NopInstruction()

uint32_t XCAP_getType2NopInstruction ( int  payload )

inline

Generate and return the encoding for a type 2 NOP instruction.

Definition at line 328 of file inlineCAP.h.

{
    return XCAP_getType2Instruction(XCAP::Operation::NOP, payload);
}

References XCAP::NOP, and XCAP_getType2Instruction().

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XCAP_getType2ReadInstruction()

uint32_t XCAP_getType2ReadInstruction ( int  payload )

inline

Generate and return the encoding for a type 2 Read instruction.

Definition at line 334 of file inlineCAP.h.

{
    return XCAP_getType2Instruction(XCAP::Operation::READ, (payload & 0x07FFFFFF));
}

References XCAP::READ, and XCAP_getType2Instruction().

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XCAP_getType2ReservedInstruction()

uint32_t XCAP_getType2ReservedInstruction ( int  payload )

inline

Generate and return the encoding for a type 2 Reserved instruction.

Definition at line 346 of file inlineCAP.h.

{
    return XCAP_getType2Instruction(XCAP::Operation::RESERVED, payload);
}

References XCAP::RESERVED, and XCAP_getType2Instruction().

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XCAP_getType2WriteInstruction()

uint32_t XCAP_getType2WriteInstruction ( int  payload )

inline

Generate and return the encoding for a type 2 Write instruction.

Definition at line 340 of file inlineCAP.h.

{
    return XCAP_getType2Instruction(XCAP::Operation::WRITE, (payload & 0x07FFFFFF));
}

References XCAP::WRITE, and XCAP_getType2Instruction().

Referenced by XCAP_writeType2().

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XCAP_IDCODEInstruction()

uint32_t XCAP_IDCODEInstruction ( )

inline

Generate and return the encoding for a IDCODE writing instruction.

Definition at line 424 of file inlineCAP.h.

{
    return XCAP_getType1WriteInstruction(XCAP::Register::IDCODE, 1);
}

References XCAP::IDCODE, and XCAP_getType1WriteInstruction().

Referenced by parseBitstreamIDCODE().

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XCAP_writeCommand()

void XCAP_writeCommand ( std::ofstream &  fout, XCAP::Command  cmd, Endianness  e  )

inline

Generate the encoding for writing a CAP command and write it to file ofstream.

Definition at line 390 of file inlineCAP.h.

{
    XCAP_writeRegister(fout, XCAP::Register::CMD, static_cast<int>(cmd), e);
}

References XCAP::CMD, and XCAP_writeRegister().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRHeaderSequence(), XilinxSeries7::outputBitstreamEmptySLRWrapUpSequence(), XilinxUltraScale::outputBitstreamEmptySLRWrapUpSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRWrapUpSequence(), XilinxSeries7::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRFooterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderBitstreamSequence(), XilinxSeries7::outputBitstreamSLRWrapUpSequence(), XilinxUltraScale::outputBitstreamSLRWrapUpSequence(), XilinxUltraScalePlus::outputBitstreamSLRWrapUpSequence(), and writeBitstreamMainSingleRegion().

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XCAP_writeFDRI()

void XCAP_writeFDRI ( std::ofstream &  fout, int  wordCount, Endianness  e  )

inline

Generate and write an FDRI command. Always uses type 2 command for simplicity.

Definition at line 417 of file inlineCAP.h.

{
    XCAP_writeFDRI1(fout, 0, e);
    XCAP_writeType2(fout, wordCount, e);
}

References XCAP_writeFDRI1(), and XCAP_writeType2().

Referenced by writeBitstreamMainSingleRegion().

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XCAP_writeFDRI1()

void XCAP_writeFDRI1 ( std::ofstream &  fout, int  wordCount, Endianness  e  )

inline

Generate and write only a type 1 FDRI command.

Definition at line 403 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1WriteInstruction(XCAP::Register::FDRI, wordCount);
    FileIO::write32(fout, instruction, e);
}

References XCAP::FDRI, FileIO::write32(), and XCAP_getType1WriteInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), and XCAP_writeFDRI().

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XCAP_writeMaskAndRegister()

void XCAP_writeMaskAndRegister ( std::ofstream &  fout, XCAP::Register  reg, int  writeMask, int  writeValue, Endianness  e  )

inline

Generate the encoding for writing a CAP register with a mask and write it to file ofstream.

Definition at line 396 of file inlineCAP.h.

{
    XCAP_writeRegister(fout, XCAP::Register::MASK, writeMask, e);
    XCAP_writeRegister(fout, reg, writeValue, e);
}

References XCAP::MASK, and XCAP_writeRegister().

Referenced by XilinxSeries7::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRFooterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence(), and XilinxUltraScalePlus::outputBitstreamSLRHeaderBitstreamSequence().

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XCAP_writeNOP()

void XCAP_writeNOP ( std::ofstream &  fout, int  cnt, int  payload, Endianness  e  )

inline

Generate the encoding for NOP instructions and write them to file ofstream.

Definition at line 352 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1NopInstruction(payload);
    for(int i = 0 ; i < cnt ; i++)
        FileIO::write32(fout, instruction, e);
}

References FileIO::write32(), and XCAP_getType1NopInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRHeaderSequence(), XilinxSeries7::outputBitstreamEmptySLRWrapUpSequence(), XilinxUltraScale::outputBitstreamEmptySLRWrapUpSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRWrapUpSequence(), XilinxSeries7::outputBitstreamGlobalFooterSequence(), XilinxUltraScale::outputBitstreamGlobalFooterSequence(), XilinxUltraScalePlus::outputBitstreamGlobalFooterSequence(), XilinxSeries7::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRFooterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderBitstreamSequence(), XilinxSeries7::outputBitstreamSLRWrapUpSequence(), XilinxUltraScale::outputBitstreamSLRWrapUpSequence(), XilinxUltraScalePlus::outputBitstreamSLRWrapUpSequence(), and writeBitstreamMainSingleRegion().

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XCAP_writeReadRegister()

void XCAP_writeReadRegister ( std::ofstream &  fout, XCAP::Register  reg, int  readLength, Endianness  e  )

inline

Generate the encoding for reading a CAP register and write it to file ofstream.

Definition at line 375 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1ReadInstruction(reg, readLength);
    FileIO::write32(fout, instruction, e);
}

References FileIO::write32(), and XCAP_getType1ReadInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), and XilinxUltraScalePlus::assemblerAsmTo().

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XCAP_writeRegister()

void XCAP_writeRegister ( std::ofstream &  fout, XCAP::Register  reg, int  writeValue, Endianness  e  )

inline

Generate the encoding for writing a CAP register and write it to file ofstream.

Definition at line 382 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1WriteInstruction(reg, 1);
    FileIO::write32(fout, instruction, e);
    FileIO::write32(fout, writeValue, e);
}

References FileIO::write32(), and XCAP_getType1WriteInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRHeaderSequence(), XilinxSeries7::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRFooterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRFooterBitstreamSequence(), XilinxSeries7::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderBitstreamSequence(), writeBitstreamMainSingleRegion(), XCAP_writeCommand(), and XCAP_writeMaskAndRegister().

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XCAP_writeRESERVED()

void XCAP_writeRESERVED ( std::ofstream &  fout, int  cnt, int  payload, Endianness  e  )

inline

Generate the encoding for Reserved instructions and write them to file ofstream.

Definition at line 360 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1ReservedInstruction(payload);
    for(int i = 0 ; i < cnt ; i++)
        FileIO::write32(fout, instruction, e);
}

References FileIO::write32(), and XCAP_getType1ReservedInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), and XilinxUltraScalePlus::assemblerAsmTo().

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XCAP_writeSelectRegister()

void XCAP_writeSelectRegister ( std::ofstream &  fout, XCAP::Register  reg, Endianness  e  )

inline

Generate the encoding for "selecting" a CAP register and write it to file ofstream.

Definition at line 368 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType1WriteInstruction(reg, 0);
    FileIO::write32(fout, instruction, e);
}

References FileIO::write32(), and XCAP_getType1WriteInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRHeaderSequence(), XilinxSeries7::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderAfterBitstreamSequence(), and XilinxUltraScalePlus::outputBitstreamSLRHeaderAfterBitstreamSequence().

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XCAP_writeSYNQ()

void XCAP_writeSYNQ ( std::ofstream &  fout, Endianness  e  )

inline

Generate and write an SYNQ command.

Definition at line 436 of file inlineCAP.h.

{
    FileIO::write32(fout, XCAP_getSyncInstruction(), e);
}

References FileIO::write32(), and XCAP_getSyncInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderAfterBitstreamSequence(), and XilinxUltraScalePlus::outputBitstreamSLRHeaderAfterBitstreamSequence().

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XCAP_writeType2()

void XCAP_writeType2 ( std::ofstream &  fout, int  wordCount, Endianness  e  )

inline

Generate and write only a type 2 FDRI command.

Definition at line 410 of file inlineCAP.h.

{
    uint32_t instruction = XCAP_getType2WriteInstruction(wordCount);
    FileIO::write32(fout, instruction, e);
}

References FileIO::write32(), and XCAP_getType2WriteInstruction().

Referenced by XilinxSeries7::assemblerAsmTo(), XilinxUltraScale::assemblerAsmTo(), XilinxUltraScalePlus::assemblerAsmTo(), XilinxSeries7::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScale::outputBitstreamEmptySLRHeaderSequence(), XilinxUltraScalePlus::outputBitstreamEmptySLRHeaderSequence(), XilinxSeries7::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScale::outputBitstreamSLRHeaderAfterBitstreamSequence(), XilinxUltraScalePlus::outputBitstreamSLRHeaderAfterBitstreamSequence(), and XCAP_writeFDRI().

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