27 #define EXECUTABLE "byteman.exe"
29 #define EXECUTABLE "byteman"
33 std::cout <<
"byteman " << VERSION <<
" (Build #" << VERSION_BUILD <<
", compiled on " << __DATE__ <<
" " << __TIME__ <<
")" << std::endl;
42 std::cout <<
"Usage:" << std::endl;
43 std::cout <<
" " EXECUTABLE " ARCH [-command...]* [-stdin]" << std::endl;
44 std::cout << std::endl;
45 std::cout <<
" ARCH = {\"Xilinx Series 7\"/\"XS7\", \"Xilinx UltraScale\"/\"XUS\", \"Xilinx UltraScale+ \"/\"XUSP\"}" << std::endl;
46 std::cout << std::endl;
47 std::cout <<
"Commands: : [Description] " << std::endl;
48 std::cout <<
" -a (Assembly) : (de)assemble bitstreams. see \"-help assembly\"" << std::endl;
49 std::cout <<
" -b (Blank) : erases bitstream buffers. see \"-help blank\"" << std::endl;
50 std::cout <<
" -c (Change) : modify bitstream. see \"-help change\"" << std::endl;
51 std::cout <<
" -d (Device) : manually select target device. see \"-help device\"" << std::endl;
52 std::cout <<
" -e (Exit) : exit byteman. used with stdin. see \"-help exit\"" << std::endl;
53 std::cout <<
" -h (Help) : get help. see \"-help help\"" << std::endl;
54 std::cout <<
" -i (Input) : input bitstream. see \"-help input\"" << std::endl;
55 std::cout <<
" -m (Merge) : merge bitstreams. see \"-help merge\"" << std::endl;
56 std::cout <<
" -o (Output) : output bitstream. see \"-help output\"" << std::endl;
57 std::cout <<
" -r (Region) : modify region selection. see \"-help region\"" << std::endl;
58 std::cout <<
" -s (Stdin) : continue using standard input. see \"-help stdin\"" << std::endl;
59 std::cout <<
" -v (Verbose) : enable/disable spam. see \"-help verbose\"" << std::endl;
60 std::cout <<
" -w (Warn) : enable/disable warnings. see \"-help warn\"" << std::endl;
61 std::cout << std::endl;
62 std::cout <<
"Examples: " << std::endl;
63 std::cout <<
" " EXECUTABLE " Xilinx US+ -w -i main static.bit -i temp filter.bit -merge logic 180:67 120:30 240:37 -o logic 240:37 120:30 relocatedFilter.bit" << std::endl;
64 std::cout <<
" " EXECUTABLE " XUSP -w -d ZCU 102 -b main, logic, blockram -i temp filter.bit -merge logic 180:67 120:30 180:67 -o logic 180:67 120:30 mergedFilter.bit" << std::endl;
65 std::cout << std::endl;
66 std::cout <<
"Need more help? Try one of these:" << std::endl;
67 std::cout <<
" " EXECUTABLE " -help <command>" << std::endl;
68 std::cout <<
" " EXECUTABLE " -help all" << std::endl;
69 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -help all" << std::endl;
70 std::cout <<
" " EXECUTABLE " Xilinx UltraScale -help all" << std::endl;
71 std::cout <<
" " EXECUTABLE " Xilinx UltraScale+ -help all" << std::endl;
117 std::cout <<
"Unknown command to help you with: \"" << param <<
"\"!" << std::endl;
118 std::cout <<
"Try one of \"assembly\", \"blank\", \"change\", \"device\", \"exit\", \"help\", \"input\", \"merge\", \"output\", \"region\", \"stdin\", \"verbose\", \"warn\" maybe?" << std::endl;
119 std::cout << std::endl;
125 std::cout <<
"byteman: Verbose" << std::endl;
126 std::cout <<
" enables/disables logging messages. they are disabled by default." << std::endl;
127 std::cout << std::endl;
128 std::cout <<
" Usage:" << std::endl;
129 std::cout <<
" " EXECUTABLE " -verbose [<VerboseValue>]" << std::endl;
130 std::cout << std::endl;
131 std::cout <<
" Arg:" << std::endl;
132 std::cout <<
" [<VerboseValue>]: accepted values are 0 to disable and 1 to enable. Default is 1." << std::endl;
133 std::cout << std::endl;
134 std::cout <<
" Examples:" << std::endl;
135 std::cout <<
" # Enable logging:" << std::endl;
136 std::cout <<
" " EXECUTABLE " XUSP -v" << std::endl;
137 std::cout << std::endl;
138 std::cout <<
" # Disable logging, but it was disabled by default anyway:" << std::endl;
139 std::cout <<
" " EXECUTABLE " Xilinx US -verbose 0" << std::endl;
140 std::cout << std::endl;
141 std::cout <<
" # Enable logging for (-...) and then disable logging again:" << std::endl;
142 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -v -... -v=0" << std::endl;
143 std::cout << std::endl;
144 std::cout << std::endl;
149 std::cout <<
"byteman: Warn" << std::endl;
150 std::cout <<
" enables/disables warning messages. they are enabled by default." << std::endl;
151 std::cout << std::endl;
152 std::cout <<
" Usage:" << std::endl;
153 std::cout <<
" " EXECUTABLE " -warn [<WarnValue>]" << std::endl;
154 std::cout << std::endl;
155 std::cout <<
" Arg:" << std::endl;
156 std::cout <<
" [<WarnValue>]: accepted values are 0 to disable and 1 to enable. Default is 1." << std::endl;
157 std::cout << std::endl;
158 std::cout <<
" Examples:" << std::endl;
159 std::cout <<
" # Enable warnings, but they were enabled by default anyway:" << std::endl;
160 std::cout <<
" " EXECUTABLE " XUSP -w" << std::endl;
161 std::cout << std::endl;
162 std::cout <<
" # Disable warnings:" << std::endl;
163 std::cout <<
" " EXECUTABLE " Xilinx US -warn 0" << std::endl;
164 std::cout << std::endl;
165 std::cout <<
" # Disable warnings for (-...) and then enable warnings again:" << std::endl;
166 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -w=0 -... -w" << std::endl;
167 std::cout << std::endl;
168 std::cout << std::endl;
173 std::cout <<
"byteman: Region" << std::endl;
174 std::cout <<
" modifies the list of selected regions." << std::endl;
175 std::cout << std::endl;
176 std::cout <<
" Usage:" << std::endl;
177 std::cout <<
" " EXECUTABLE " -region [Clear, Add <SrcY> <SrcX> <SizeY> <SizeX>]" << std::endl;
178 std::cout << std::endl;
179 std::cout <<
" Args:" << std::endl;
180 std::cout <<
" [Clear]: clears the selected regions list." << std::endl;
181 std::cout <<
" [Add]: adds a new rect (<SrcY>:<SrcX> <SizeY>:<SizeX>) in the selected regions list." << std::endl;
182 std::cout << std::endl;
183 std::cout <<
" Examples:" << std::endl;
184 std::cout <<
" # Clears the list:" << std::endl;
185 std::cout <<
" " EXECUTABLE " XUSP -region clear" << std::endl;
186 std::cout << std::endl;
187 std::cout <<
" # Adds a rectangle describing Y from 100 to 149 and X from 7 to 21.:" << std::endl;
188 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -r add 100:7 50:15" << std::endl;
189 std::cout << std::endl;
190 std::cout <<
" # Adds a rectangle describing Y from 120 to 179 and X from 7 to 21:" << std::endl;
191 std::cout <<
" " EXECUTABLE " Xilinx US -r add 120:7 60:15." << std::endl;
192 std::cout << std::endl;
193 std::cout << std::endl;
198 std::cout <<
"byteman: Blank" << std::endl;
199 std::cout <<
" erases/sets the bitstream in the buffers. uses the list of selected regions (see \"-help Region\"). if the list is empty, works on the whole chip." << std::endl;
200 std::cout << std::endl;
201 std::cout <<
" Usage:" << std::endl;
202 std::cout <<
" " EXECUTABLE " -blank [First] [Second] [Logic] [Clock] [BlockRAM] [<BlankValue>]" << std::endl;
203 std::cout << std::endl;
204 std::cout <<
" Args:" << std::endl;
205 std::cout <<
" [First]: selects the first of the two bitstream buffers. Enabled by default if no buffer is explicitly specified." << std::endl;
206 std::cout <<
" [Second]: selects the second of the two bitstream buffers." << std::endl;
207 std::cout <<
" [Logic]: selects the data excluding global clock from logic plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
208 std::cout <<
" [Clock]: selects the global clock data from logic plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
209 std::cout <<
" [BlockRAM]: selects the blockram contents plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
210 std::cout <<
" [<BlankValue>]: byte value (0-255) to be written in the selected bitstream location. Default is 0." << std::endl;
211 std::cout << std::endl;
212 std::cout <<
" Examples:" << std::endl;
213 std::cout <<
" # Blanks the bitstream's logic plane to zeroes:" << std::endl;
214 std::cout <<
" " EXECUTABLE " XUSP -blank main clb" << std::endl;
215 std::cout << std::endl;
216 std::cout <<
" # All values in the rectangle describing Y from 100 to 149 and X from 7 to 21 are set to 0xA5A5A5A5:" << std::endl;
217 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -r add 100:7 50:15 -b 0xA5" << std::endl;
218 std::cout << std::endl;
219 std::cout <<
" # Blanks the bitstream to zeroes:" << std::endl;
220 std::cout <<
" " EXECUTABLE " Xilinx US -b" << std::endl;
221 std::cout << std::endl;
222 std::cout << std::endl;
227 std::cout <<
"byteman: Change" << std::endl;
228 std::cout <<
" modifies bitstream data." << std::endl;
229 std::cout << std::endl;
230 std::cout <<
" Usage:" << std::endl;
231 std::cout <<
" " EXECUTABLE " -change [First] [Second] [BigEndian, LittleEndian, BigEndianWithBitSwap, LittleEndianWithBitSwap, NativeEndian] [word <Y>:<X> <blockType> <frameOffset> <wordOffset> <mask> <value>]" << std::endl;
232 std::cout << std::endl;
233 std::cout <<
" Args:" << std::endl;
234 std::cout <<
" [First]: selects the first of the two bitstream buffers. Enabled by default if no buffer is explicitly specified." << std::endl;
235 std::cout <<
" [Second]: selects the second of the two bitstream buffers." << std::endl;
236 std::cout <<
" [BigEndian]: forces the stored bitstream data is in Big Endian format. any future operations will inherit the endianness (such as -Output)" << std::endl;
237 std::cout <<
" [LittleEndian]: forces the stored bitstream data is in Little Endian format. any future operations will inherit the endianness (such as -Output)" << std::endl;
238 std::cout <<
" [BigEndianWithBitSwap]: forces the stored bitstream data is in Big Endian with Bit Swap format. any future operations will inherit the endianness (such as -Output)" << std::endl;
239 std::cout <<
" [LittleEndianWithBitSwap]: forces the stored bitstream data is in Little Endian with Bit Swap format. any future operations will inherit the endianness (such as -Output)" << std::endl;
240 std::cout <<
" [NativeEndian]: forces the stored bitstream data is in the native endianness of the system. any future operations will inherit the endianness (such as -Output)" << std::endl;
241 std::cout <<
" [word <Y>:<X> <blockType> <frameOffset> <wordOffset> <mask> <value>]: forces bitstream value <value> (masked by <mask>) to a word located at coordinates <Y>:<X> in block <blockType>" << std::endl;
242 std::cout <<
" : with internal offsets for the frame <frameOffset> and word <wordOffset>" << std::endl;
243 std::cout << std::endl;
244 std::cout <<
" Examples:" << std::endl;
245 std::cout <<
" # reads a bitstream, forces big endianness, writes back the bitstream in the new endianness:" << std::endl;
246 std::cout <<
" " EXECUTABLE " XUS -input bitstream.bit -change bigEndian -output full bitstream.bit" << std::endl;
247 std::cout <<
" # reads a bitstream, forces little endianness, writes back the bitstream in the new endianness:" << std::endl;
248 std::cout <<
" " EXECUTABLE " xilinx series 7 -input boot.bin -change LITTLEendian -output full boot.bin" << std::endl;
249 std::cout <<
" # load a partial bitstream located at 180:0. targetting the third blockram left to right, located at 180:37." << std::endl;
250 std::cout <<
" # modify its routing at the 3rd frame (frame offset 2) at the 41-st word (word offset 40) to value 0xA5A50000 (masked by 0xFFFF0000). (the blockram routing is located in CLB block Type - blockType 0):" << std::endl;
251 std::cout <<
" " EXECUTABLE " xilinx UltraScale+ -device ZCU102 -input pr.bit -change word 180:37 0 2 40 0xFFFF0000 0xA5A50000 -output ..." << std::endl;
252 std::cout <<
" # load a partial bitstream located at 180:0. targetting the second blockram left to right, located at 180:37." << std::endl;
253 std::cout <<
" # modify contents at the 233rd frame (frame offset 232) at the 5-th word (word offset 4) to value 0xFFFFFFFF (masked by 0xFFFFFFFF). (the blockram contents are located in blockType 1):" << std::endl;
254 std::cout <<
" " EXECUTABLE " xilinx UltraScale+ -device ZCU102 -input pr.bit -change word 180:37 1 232 4 0xFFFFFFFF 0xFFFFFFFF -output ..." << std::endl;
255 std::cout << std::endl;
256 std::cout << std::endl;
257 std::cout << std::endl;
262 std::cout <<
"byteman: Device" << std::endl;
263 std::cout <<
" Sets the target device manually." << std::endl;
264 std::cout << std::endl;
265 std::cout <<
" Usage:" << std::endl;
266 std::cout <<
" " EXECUTABLE " -device [First] [Second] <DeviceName>" << std::endl;
267 std::cout << std::endl;
268 std::cout <<
" Args:" << std::endl;
269 std::cout <<
" [First]: selects the first of the two bitstream buffers. Enabled by default if no buffer is explicitly specified." << std::endl;
270 std::cout <<
" [Second]: selects the second of the two bitstream buffers." << std::endl;
271 std::cout <<
" <DeviceName>: name of the target chip, package, or board." << std::endl;
272 std::cout << std::endl;
273 std::cout <<
" Examples:" << std::endl;
274 std::cout <<
" " EXECUTABLE " XUSP -device Alveo U200" << std::endl;
275 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -d Wizarde" << std::endl;
276 std::cout <<
" " EXECUTABLE " Xilinx US -d xcvu440" << std::endl;
277 std::cout << std::endl;
280 mainXS7.deviceHelp();
284 mainXUS.deviceHelp();
288 mainXUSP.deviceHelp();
290 std::cout << std::endl;
291 std::cout << std::endl;
296 std::cout <<
"byteman: Help" << std::endl;
297 std::cout <<
" prints these messages... help messages can change if architecture and/or specific device is selected to incorporate more information!" << std::endl;
298 std::cout << std::endl;
299 std::cout <<
" Usage:" << std::endl;
300 std::cout <<
" " EXECUTABLE " -help [Command]" << std::endl;
301 std::cout << std::endl;
302 std::cout <<
" Arg:" << std::endl;
303 std::cout <<
" [Command]: prints extra information about the usage of a specific command." << std::endl;
304 std::cout << std::endl;
305 std::cout <<
" Examples:" << std::endl;
306 std::cout <<
" " EXECUTABLE " Xilinx US+ -device Alveo U200 -help device #will print extra information about the selected device" << std::endl;
307 std::cout <<
" " EXECUTABLE " Xilinx US+ -input bitfile.bit -help device #will print extra information about the bitstream device" << std::endl;
308 std::cout <<
" " EXECUTABLE " -help" << std::endl;
309 std::cout <<
" " EXECUTABLE " XUSP -h" << std::endl;
310 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -h" << std::endl;
311 std::cout <<
" " EXECUTABLE " Xilinx US -h" << std::endl;
312 std::cout <<
" " EXECUTABLE " -help help" << std::endl;
313 std::cout <<
" " EXECUTABLE " -help assembly" << std::endl;
314 std::cout <<
" " EXECUTABLE " -help blank" << std::endl;
315 std::cout <<
" " EXECUTABLE " -help change" << std::endl;
316 std::cout <<
" " EXECUTABLE " -help end" << std::endl;
317 std::cout <<
" " EXECUTABLE " -help input" << std::endl;
318 std::cout <<
" " EXECUTABLE " -help merge" << std::endl;
319 std::cout <<
" " EXECUTABLE " -help region" << std::endl;
320 std::cout <<
" " EXECUTABLE " -help output" << std::endl;
321 std::cout <<
" " EXECUTABLE " -help verbose" << std::endl;
322 std::cout <<
" " EXECUTABLE " -help warn" << std::endl;
323 std::cout <<
" " EXECUTABLE " -help device" << std::endl;
324 std::cout << std::endl;
325 std::cout << std::endl;
330 std::cout <<
"byteman: Input" << std::endl;
331 std::cout <<
" reads a bitstream from a file." << std::endl;
332 std::cout << std::endl;
333 std::cout <<
" Usage:" << std::endl;
334 std::cout <<
" " EXECUTABLE " -input [First] [Second] <InputFileName>" << std::endl;
335 std::cout << std::endl;
336 std::cout <<
" Args:" << std::endl;
337 std::cout <<
" [First]: selects the first of the two bitstream buffers. Enabled by default if no buffer is explicitly specified." << std::endl;
338 std::cout <<
" [Second]: selects the second of the two bitstream buffers." << std::endl;
339 std::cout <<
" <InputFileName>: name of the input file. supports \".bit\" and \".bin\" file formats." << std::endl;
340 std::cout << std::endl;
341 std::cout <<
" Examples:" << std::endl;
342 std::cout <<
" " EXECUTABLE " XUSP -i main zcu102bitstream.bit" << std::endl;
343 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -input zedboardBitstream.bin" << std::endl;
344 std::cout <<
" " EXECUTABLE " Xilinx US -i xcvu440Bitstream.bit" << std::endl;
345 std::cout << std::endl;
346 std::cout << std::endl;
351 std::cout <<
"byteman: Merge" << std::endl;
352 std::cout <<
" merges portion of the bitstream in the second buffer into the first buffer." << std::endl;
353 std::cout << std::endl;
354 std::cout <<
" Usage:" << std::endl;
355 std::cout <<
" " EXECUTABLE " -merge [Logic] [BlockRAM] [Clock] [SET, XOR, OR, AND] [Full, <SrcY> <SrcX> <SizeY> <SizeX> <DstY> <DstX>]" << std::endl;
356 std::cout << std::endl;
357 std::cout <<
" Args:" << std::endl;
358 std::cout <<
" [Logic]: selects the data from the logic plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
359 std::cout <<
" [Clock]: selects the global clock data from the logic plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
360 std::cout <<
" [BlockRAM]: selects the BlockRAM contents plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
361 std::cout <<
" [SET, XOR, OR, AND]: selects merge operation. XOR, OR, AND are bitwise operations. Default is \"SET\"." << std::endl;
362 std::cout <<
" [Full]: selects the full device bitstream." << std::endl;
363 std::cout <<
" [<SrcY> <SrcX> <SizeY> <SizeX> <DstY> <DstX>]: selects a rect (<SrcY> <SrcX> <SizeY> <SizeX>) from the second bitstream buffer to be merged" << std::endl;
364 std::cout <<
" : into destination rect (<DstY> <DstX> <SizeY> <SizeX>) in first bitstream buffer." << std::endl;
365 std::cout << std::endl;
366 std::cout <<
" Examples:" << std::endl;
367 std::cout <<
" # Copies second bitstream into first bitstream's buffer:" << std::endl;
368 std::cout <<
" " EXECUTABLE " XUSP -input bit1.bit -input second bit2.bin -merge full" << std::endl;
369 std::cout << std::endl;
370 std::cout <<
" # A rect in second buffer (Y from 50 to 99 and X from 10 to 29) is bitwise XORed in the clock and blockram" << std::endl;
371 std::cout <<
" # contents planes into a rect in 1st buffer describing Y from 100 to 149 and X from 30 to 49:" << std::endl;
372 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -... -merge clock, bram, xor 50:10 50:20 100:30" << std::endl;
373 std::cout << std::endl;
374 std::cout <<
" # Copies the logic plane from buffer 2 into buffer 1:" << std::endl;
375 std::cout <<
" " EXECUTABLE " Xilinx US -... -m full, logic" << std::endl;
376 std::cout << std::endl;
377 std::cout << std::endl;
382 std::cout <<
"byteman: Output" << std::endl;
383 std::cout <<
" creates a bitstream file output from the first bitstream buffer in byteman." << std::endl;
384 std::cout << std::endl;
385 std::cout <<
" Usage:" << std::endl;
386 std::cout <<
" " EXECUTABLE " -output [Logic] [BlockRAM] [Blank] [Full, <StartY> <StartX> <SizeY> <SizeX>] <OutputFileName>" << std::endl;
387 std::cout << std::endl;
388 std::cout <<
" Args:" << std::endl;
389 std::cout <<
" [Logic]: selects the logic plane (incl global clock) of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
390 std::cout <<
" [BlockRAM]: selects the BlockRAM contents plane of the bitstream. Enabled by default if no plane is explicitly specified." << std::endl;
391 std::cout <<
" [Blank]: blanks the selected regions to zeroes before writing the actual bitstream to them." << std::endl;
392 std::cout <<
" [Full]: selects all frames in the chip." << std::endl;
393 std::cout <<
" [<StartY> <StartX> <SizeY> <SizeX>]: selects a rect (<StartY> <StartX> <SizeY> <SizeX>) for output." << std::endl;
394 std::cout <<
" : also the list of selected regions will be output (see \"byteman -help Region\")." << std::endl;
395 std::cout <<
" <OutputFileName>: name of the output file. supports \".bit\" and \".bin\" file formats." << std::endl;
396 std::cout << std::endl;
397 std::cout <<
" Examples:" << std::endl;
398 std::cout <<
" # Output only the blockram contents to the whole FPGA:" << std::endl;
399 std::cout <<
" " EXECUTABLE " XUSP -input bitstream.bit -... -output bram, full bitfil.bit" << std::endl;
400 std::cout << std::endl;
401 std::cout <<
" # The rectangle describing Y from 50 to 99 and X from 10 to 29 is zeroed and then the logic plane bitstream data is written:" << std::endl;
402 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -... -o logic, blank 50:10 50:20 bitstream.bin" << std::endl;
403 std::cout << std::endl;
404 std::cout <<
" # The rectangles (60:10 120:20 and 180:30 240:40) are zeroed and the logic & blockram content planes are written:" << std::endl;
405 std::cout <<
" " EXECUTABLE " XUS -... -r add 60:10 120:20 -o blank 180:30 240:40 fo.bit" << std::endl;
406 std::cout << std::endl;
407 std::cout << std::endl;
412 std::cout <<
"byteman: Assembly" << std::endl;
413 std::cout <<
" assembles and disassembles between bitstream files (.bit|.bin) and bitstream assembly (.bitasm) format." << std::endl;
414 std::cout << std::endl;
415 std::cout <<
" Usage:" << std::endl;
416 std::cout <<
" " EXECUTABLE " -assembly <InputBitstreamFileName> <OutputAssemblyFileName>" << std::endl;
417 std::cout <<
" " EXECUTABLE " -assembly <InputAssemblyFileName> <OutputBitstreamFileName>" << std::endl;
418 std::cout <<
" Args:" << std::endl;
419 std::cout <<
" <InputBitstreamFileName>: name of the input bitstream file. supports \".bit\" and \".bin\" file formats." << std::endl;
420 std::cout <<
" <OutputBitstreamFileName>: name of the output bitstream file. supports \".bit\" and \".bin\" file formats." << std::endl;
421 std::cout <<
" <InputAssemblyFileName>: name of the input assembly file. supports \".bitasm\" file format." << std::endl;
422 std::cout <<
" <OutputAssemblyFileName>: name of the output assembly file. supports \".bitasm\" file format." << std::endl;
423 std::cout << std::endl;
424 std::cout <<
" the bitstream assembly files can be edited and converted back to valid bitstreams." << std::endl;
425 std::cout <<
" in bitstream assembly file format:" << std::endl;
426 std::cout <<
" every line that doesn't start with '#' is editable." << std::endl;
427 std::cout <<
" bitstream commands are written one per line and have the format \"<COMMAND NAME>;\"" << std::endl;
428 std::cout <<
" bitstream register writesare one per line and have the format \"@<REGNAME> = <NEW REG VALUE>\"" << std::endl;
429 std::cout << std::endl;
430 std::cout <<
" Examples:" << std::endl;
431 std::cout <<
" " EXECUTABLE " XUSP -assembly bitstream.bit bitstream.bitasm" << std::endl;
432 std::cout << std::endl;
433 std::cout <<
" " EXECUTABLE " Xilinx Series 7 -a bitstream.bitasm bitstream.bit" << std::endl;
434 std::cout << std::endl;
435 std::cout <<
" # Generate a bitstream file and then convert it to bit assembly:" << std::endl;
436 std::cout <<
" " EXECUTABLE " Xilinx US -... -o bitstreamOut.bit -a bitstreamOut.bit bitstreamOut.bitasm" << std::endl;
437 std::cout << std::endl;
438 std::cout << std::endl;
443 std::cout <<
"byteman: Exit" << std::endl;
444 std::cout <<
" finishes execution of byteman. used with STDin mode (see \"-help STDin\") to identify the end of command sequence." << std::endl;
445 std::cout << std::endl;
446 std::cout << std::endl;
451 std::cout <<
"byteman: STDin" << std::endl;
452 std::cout <<
" continues reading commands from standard input rather than command line arguments. this way commands can be entered by hand or streamed in by another program or file." << std::endl;
453 std::cout << std::endl;
454 std::cout <<
" Usage:" << std::endl;
455 std::cout <<
" " EXECUTABLE " [commands]* -stdin" << std::endl;
456 std::cout << std::endl;
457 std::cout <<
" the input supports the following format rules:" << std::endl;
458 std::cout <<
" all commands are the same as their command line argument counterparts." << std::endl;
459 std::cout <<
" one command (with its arguments) per line." << std::endl;
460 std::cout <<
" '-' at the beginning of a command can be skipped." << std::endl;
461 std::cout <<
" '#' starts a comments until a new line is seen." << std::endl;
462 std::cout <<
" the command Exit will end reading the input stream and close byteman." << std::endl;
463 std::cout << std::endl;
464 std::cout << std::endl;
void helpVerbose(bool=false)
void helpBlank(bool=false)
enum byteman::Architecture selectedArchitecture
void helpStdin(bool=false)
void helpDevice(bool=false)
void helpMerge(bool=false)
void helpExit(bool=false)
void helpOutput(bool=false)
void helpHelp(bool=false)
void helpWarn(bool=false)
void helpAssembly(bool=false)
void helpChange(bool=false)
void helpRegion(bool=false)
void helpInput(bool=false)
bool stringIs(std::string checkedString)
Returns false. End of recursion for template.