XilinxUltraScale Member List

This is the complete list of members for XilinxUltraScale, including all inherited members.

assembler(std::string, std::string)	XilinxUltraScale
assemblerAsmTo(std::ifstream &, std::ofstream &)	XilinxUltraScale
assemblerAsmToBin(std::ifstream &, std::ofstream &)	XilinxUltraScale
assemblerAsmToBit(std::ifstream &, std::ofstream &)	XilinxUltraScale
assemblerParseHeader(std::ifstream &)	XilinxUltraScale
bitstreamBegin	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
bitstreamBRAM	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
bitstreamCLB	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
bitstreamEnd	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
bitstreamHasValidData	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
blank(std::string)	XilinxUltraScale
change(std::string)	XilinxUltraScale
CommonDevice()	CommonDevice	inline
CommonDevice2D()	CommonDevice2D	inline
designName	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
deviceHelp()	XilinxUltraScale
disassemblerBinToAsm(std::string, std::ifstream &, std::ofstream &)	XilinxUltraScale
disassemblerBitToAsm(std::ifstream &, std::ofstream &)	XilinxUltraScale
disassemblerToAsm(std::ifstream &, std::ofstream &)	XilinxUltraScale
disassemblerWriteHeader(std::ofstream &)	XilinxUltraScale
enableLog	CommonDevice
enableWarn	CommonDevice
ensureInitializedBitstreamArrays() override	XilinxUltraScale	virtual
fileDate	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
fileTime	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
fromRow	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
getDeviceByIDCODE(int) override	XilinxUltraScale	virtual
getDeviceByIDCODEorThrow(int) override	XilinxUltraScale	virtual
getDeviceByName(std::string) override	XilinxUltraScale	virtual
getDeviceByNameOrThrow(std::string) override	XilinxUltraScale	virtual
getFrameType(int, int, int) override	XilinxUltraScale	virtual
headerLocationOfRemainingFileLength	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
IDCODE	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
initFabric()	XilinxUltraScale
initializedBitstreamParamsShortPartName	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
initializedBitstreamShortPartName	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
initializedResourceStringShortPartName	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
initializeResourceStringParameters() override	XilinxUltraScale	virtual
instanceName	CommonDevice
loadedBitstreamEndianness	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
log(std::string message)	CommonDevice	inline
LUT_isFrameUnusedForResourceLetter	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
LUT_numberOfFramesForResourceLetter	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
LUT_typeOfFrameForResourceLetter	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
maxNumberOfBRAMCols	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
maxNumberOfCols	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
merge(XilinxUltraScale *, std::string, Rect2D, Coord2D)	XilinxUltraScale
MergeOP enum name	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfBRAMCols	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfBRAMsBeforeCol	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfCols	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfFramesBeforeCol	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfFramesPerRow	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfRows	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfSLRs	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
numberOfWordsPerRow	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
outputBitstreamEmptySLRHeaderSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamEmptySLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamGlobalFooterSequence(std::ofstream &, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamGlobalHeaderSequence(std::ofstream &, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamSLRFooterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamSLRHeaderAfterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamSLRHeaderBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
outputBitstreamSLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScale	virtual
partName	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
printMessage(std::string message)	CommonDevice	inline
readBitstream(std::string)	XilinxUltraScale
region(std::string, Rect2D)	CommonDevice2D
regionSelection	CommonDevice2D
resourceString	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
rowsInBottomHalf	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
rowsInTopHalf	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
selectedOptions	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
setDevice(int, std::string="") override	XilinxUltraScale	virtual
setDeviceByIDCODEOrThrow(int) override	XilinxUltraScale	virtual
setDeviceByNameOrThrow(std::string) override	XilinxUltraScale	virtual
setDeviceByPartNameOrThrow() override	XilinxUltraScale	virtual
SLRinfo	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
slrMagicInstrLocation	XilinxUltraScale
test(bool, bool, uint32_t)	XilinxUltraScale
toRow	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >
warn(std::string message)	CommonDevice	inline
writeBitstream(std::string, std::string, Rect2D)	XilinxUltraScale
XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >	inline
XilinxUltraScale()	XilinxUltraScale
~CommonDevice()	CommonDevice	inlinevirtual
~CommonDevice2D()	CommonDevice2D	inlinevirtual
~XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 3, 15, 1024, 32, 2, 0, 1, 60, 3, 60,(60+3+60), 128, 60, 12, 2, 0, 0, 23, 0x7, 17, 0x3F, 7, 0x3FF, 0, 0x7F >	inlinevirtual
~XilinxUltraScale()	XilinxUltraScale	virtual