XilinxSeries7 Member List

This is the complete list of members for XilinxSeries7, including all inherited members.

assembler(std::string, std::string)	XilinxSeries7
assemblerAsmTo(std::ifstream &, std::ofstream &)	XilinxSeries7
assemblerAsmToBin(std::ifstream &, std::ofstream &)	XilinxSeries7
assemblerAsmToBit(std::ifstream &, std::ofstream &)	XilinxSeries7
assemblerParseHeader(std::ifstream &)	XilinxSeries7
bitstreamBegin	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
bitstreamBRAM	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
bitstreamCLB	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
bitstreamEnd	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
bitstreamHasValidData	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
blank(std::string)	XilinxSeries7
change(std::string)	XilinxSeries7
CommonDevice()	CommonDevice	inline
CommonDevice2D()	CommonDevice2D	inline
designName	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
deviceHelp()	XilinxSeries7
disassemblerBinToAsm(std::string, std::ifstream &, std::ofstream &)	XilinxSeries7
disassemblerBitToAsm(std::ifstream &, std::ofstream &)	XilinxSeries7
disassemblerToAsm(std::ifstream &, std::ofstream &)	XilinxSeries7
disassemblerWriteHeader(std::ofstream &)	XilinxSeries7
enableLog	CommonDevice
enableWarn	CommonDevice
ensureInitializedBitstreamArrays() override	XilinxSeries7	virtual
fileDate	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
fileTime	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
fromRow	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
getDeviceByIDCODE(int) override	XilinxSeries7	virtual
getDeviceByIDCODEorThrow(int) override	XilinxSeries7	virtual
getDeviceByName(std::string) override	XilinxSeries7	virtual
getDeviceByNameOrThrow(std::string) override	XilinxSeries7	virtual
getFrameType(int, int, int) override	XilinxSeries7	virtual
headerLocationOfRemainingFileLength	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
IDCODE	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
initFabric()	XilinxSeries7
initializedBitstreamParamsShortPartName	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
initializedBitstreamShortPartName	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
initializedResourceStringShortPartName	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
initializeResourceStringParameters() override	XilinxSeries7	virtual
instanceName	CommonDevice
loadedBitstreamEndianness	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
log(std::string message)	CommonDevice	inline
LUT_isFrameUnusedForResourceLetter	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
LUT_numberOfFramesForResourceLetter	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
LUT_typeOfFrameForResourceLetter	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
maxNumberOfBRAMCols	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
maxNumberOfCols	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
merge(XilinxSeries7 *, std::string, Rect2D, Coord2D)	XilinxSeries7
MergeOP enum name	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfBRAMCols	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfBRAMsBeforeCol	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfCols	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfFramesBeforeCol	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfFramesPerRow	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfRows	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfSLRs	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
numberOfWordsPerRow	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
outputBitstreamEmptySLRHeaderSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamEmptySLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamGlobalFooterSequence(std::ofstream &, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamGlobalHeaderSequence(std::ofstream &, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamSLRFooterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamSLRHeaderAfterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamSLRHeaderBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
outputBitstreamSLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxSeries7	virtual
partName	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
printMessage(std::string message)	CommonDevice	inline
readBitstream(std::string)	XilinxSeries7
region(std::string, Rect2D)	CommonDevice2D
regionSelection	CommonDevice2D
resourceString	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
rowsInBottomHalf	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
rowsInTopHalf	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
selectedOptions	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
setDevice(int, std::string="") override	XilinxSeries7	virtual
setDeviceByIDCODEOrThrow(int) override	XilinxSeries7	virtual
setDeviceByNameOrThrow(std::string) override	XilinxSeries7	virtual
setDeviceByPartNameOrThrow() override	XilinxSeries7	virtual
SLRinfo	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
slrMagicInstrLocation	XilinxSeries7
test(bool, bool, uint32_t)	XilinxSeries7
toRow	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >
warn(std::string message)	CommonDevice	inline
writeBitstream(std::string, std::string, Rect2D)	XilinxSeries7
XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >	inline
XilinxSeries7()	XilinxSeries7
~CommonDevice()	CommonDevice	inlinevirtual
~CommonDevice2D()	CommonDevice2D	inlinevirtual
~XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 5, 12, 512, 32, 2, 0, 1, 50, 1, 50,(50+1+50), 128, 50, 10, 2, 1, 22, 23, 0x7, 17, 0x1F, 7, 0x3FF, 0, 0x7F >	inlinevirtual
~XilinxSeries7()	XilinxSeries7	virtual